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'[PIC]: F628 UART and intrc'
2002\02\26@023110 by Terence Ang

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Hi,
   I will be receiving my batch of F628 soon, need to find out :-

1) If I use intrc can I still use the UART ???

2) what will the be the maximum length of wire I can run between 2 F628 UART
without any extra hardware.

Thank in advance.


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Terence Ang

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2002\02\26@040931 by Vasile Surducan

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On Tue, 26 Feb 2002, Terence Ang wrote:

> Hi,
>     I will be receiving my batch of F628 soon, need to find out :-
>
> 1) If I use intrc can I still use the UART ???
>
> 2) what will the be the maximum length of wire I can run between 2 F628 UART
> without any extra hardware.
>
 twisted wire pairs: tx and gnd, rx and gnd no problem at 2 m at 19200.
 there wasn't any serious perturber powered at mains ( power switching
mode lasers, etc )

Vasile

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2002\02\26@074619 by Olin Lathrop

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> 1) If I use intrc can I still use the UART ???

This is strictly a matter of timing tolerance between the two devices on the
line.  The receiver looks for the leading edge of the start bit, then times
the other bits relative to that.  At 8 data bits, the center of the last bit
is 8 1/2 bits from the leading edge of the start bit.  The absolute maximum
tolerable error is therefore 5.88%, which causes the last data bit to be
sampled at its edge instead of the middle.  Most receivers sync everything
to a 16x baud clock, so there is an additional small uncertainty in
measuring the leading edge of the stop bit.  Of course, you don't want to be
near the guaranteed to fail limit anyway.  I like to see no more than about
1/4 bit time error by the last bit, or about 3% clock mismatch betwen
receiver and transmitter.

Keep in mind that this is the combined error between receiver and
transmitter.  If you know the other end is right on (like a PC, for
example), then you can get away with 3% mismatch in the PIC.  If you've got
two PICs with uncertain oscillators, then they each need to be within 1.5%.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, spam_OUTolinTakeThisOuTspamembedinc.com, http://www.embedinc.com

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2002\02\26@085839 by Byron A Jeff

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On Tue, Feb 26, 2002 at 03:30:12PM +0800, Terence Ang wrote:
> Hi,
>     I will be receiving my batch of F628 soon, need to find out :-
>
> 1) If I use intrc can I still use the UART ???

The grief saving answer is no. The true answer is "maybe if the conditions
are right." Conditions being that the bit rate is slow enough and there
isn't drastic changes in temperature. As an experiment set your bit rate low
(like 300 BPS or thereabouts) and start transmitting bidirectional streams
between the two PICS. Then heat one and cool the the other. If the streams
screw up, then it's probably not going to work in practice. Keep lowering
the bit rate until it stabilizes even when one PIC is ice cold (slowing the
INTRC) and the other one is really warm (speeding INTRC up). If they can
work through that disparaity, then you'll probably be all right.


>
> 2) what will the be the maximum length of wire I can run between 2 F628 UART
> without any extra hardware.

Again the grief saving answer is "not far enough" ;-) This is an instance
where I'd think about throwing a couple of nickel components at the problem.
First I'd consider a couple of EIA485 transceivers. Then you can not worry
about distance. The other I'd consider is a current loop along the lines of
a MIDI OUT/MIDI IN. It takes little more than and jellybean transistor and
an optoisolator. Easily good for 5 meters at 31250 BPS.

You're going to have to decided how much crap you willing to take out of a
very shaky setup before starting to stabilize it.

Good Luck,

BAJ

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2002\02\26@092444 by Terence Ang

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Thank for all the answers, I think I stick to resonator and RS485, I think I
am going to implement 1 master multiple slave on a half duplex mode, I think
that shouldn't be a bigger headache than unreliable comms.

On 2/26/02 8:28 PM, "Olin Lathrop" <.....olin_piclistKILLspamspam@spam@EMBEDINC.COM> wrote:

{Quote hidden}

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2002\02\26@120746 by Olin Lathrop

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> The grief saving answer is no. The true answer is "maybe if the conditions
> are right." Conditions being that the bit rate is slow enough and there
> isn't drastic changes in temperature.

The absolute bit speed has nothing to do with it.  The relative speed error
is what matters.  You'd like to be within 3%, whether that's 300 baud +-9,
or 115.2Kbaud +- 3500.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, .....olinKILLspamspam.....embedinc.com, http://www.embedinc.com

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2002\02\26@132101 by Byron A Jeff

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On Tue, Feb 26, 2002 at 10:36:00AM -0500, Olin Lathrop wrote:
> > The grief saving answer is no. The true answer is "maybe if the conditions
> > are right." Conditions being that the bit rate is slow enough and there
> > isn't drastic changes in temperature.
>
> The absolute bit speed has nothing to do with it.  The relative speed error
> is what matters.  You'd like to be within 3%, whether that's 300 baud +-9,
> or 115.2Kbaud +- 3500.

But if you slow it down then the absolute amount of time before the error
is exceeded is lengthned.

Change your examples to a time scale by inverting:

300 bPS cell width: 3.3333 ms +- 0.3ms
115k bPS cell width: 0.00886805 mS +- 0.000256 ms

There's several orders of magnitude more error available at the slower speed
before you get bit errors.

So yes absolute bit speed does have something to do with it because you
can get proper reception at 300 bPS far outside the error range for 115kbPS.

BAJ

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2002\02\26@170425 by Tony Nixon

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Terence Ang wrote:
>
> Hi,
>     I will be receiving my batch of F628 soon, need to find out :-
>
> 1) If I use intrc can I still use the UART ???

The only way I could implement it was a maximum of 9600 baud, but had to
be send byte ACK send byte ACK etc..., otherwise it screwed up.

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Tony

mICros
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2002\02\26@180148 by David Duffy

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Terrence wrote:
>Hi,
>     I will be receiving my batch of F628 soon, need to find out :-
>
>1) If I use intrc can I still use the UART ???

I have used intrc on 12cxx parts (bit banged 2400 rx) with no drama.
The PIC sending the data to them used a 4MHz resonator though.
Regards...

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2002\02\26@180747 by David Duffy

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At 01:18 PM 26/02/2002 -0500, you wrote:
{Quote hidden}

Huh?? With the faster baud rate, the byte is over quicker so it's still
relative.
Every new byte is re-synced so the error is only over one byte. The percentage
of clock error is applied to both cases equally. 3% seems to be acceptable.

>So yes absolute bit speed does have something to do with it because you
>can get proper reception at 300 bPS far outside the error range for 115kbPS.

No, this would have more to do with line conditions. (noise,etc.)
Regards...

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2002\02\26@180755 by Olin Lathrop

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> But if you slow it down then the absolute amount of time before the error
> is exceeded is lengthned.

Yes, but the absolute time error is also lengthened by the same factor.

> Change your examples to a time scale by inverting:
>
> 300 bPS cell width: 3.3333 ms +- 0.3ms
> 115k bPS cell width: 0.00886805 mS +- 0.000256 ms
>
> There's several orders of magnitude more error available at the slower
speed
> before you get bit errors.

So what!?  3% is still 3%.  At the lower speed both the error and the error
tolerance are longer in absolute time.  A 5.88% speed error is still the
absolute upper limit regardless of bit rate.

The speed only matters if something is taking a finite amount of time per
bit, like the high to low transition of a gate.  The assumption here is that
we are using a slow enough bit rate so that these can be ignored, which is
certainly true at a few tens of thousands of bits/second.


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Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olinspamspam_OUTembedinc.com, http://www.embedinc.com

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2002\02\26@182519 by Dwayne Reid

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At 01:18 PM 2/26/02 -0500, Byron A Jeff wrote:
>On Tue, Feb 26, 2002 at 10:36:00AM -0500, Olin Lathrop wrote:
> > > The grief saving answer is no. The true answer is "maybe if the
> conditions
> > > are right." Conditions being that the bit rate is slow enough and there
> > > isn't drastic changes in temperature.
> >
> > The absolute bit speed has nothing to do with it.  The relative speed error
> > is what matters.  You'd like to be within 3%, whether that's 300 baud +-9,
> > or 115.2Kbaud +- 3500.
>
>But if you slow it down then the absolute amount of time before the error
>is exceeded is lengthned.
>
>Change your examples to a time scale by inverting:
>
>300 bPS cell width: 3.3333 ms +- 0.3ms
>115k bPS cell width: 0.00886805 mS +- 0.000256 ms

Byron - please forgive me for disagreeing with you.  Olin is more correct
than you.

The baud rate is directly related to Fosc.  If Fosc changes by 1%, so does
the baud rate.  You are correct in that one can have a slight amount more
error at higher baud rates because of rounding error but that is a problem
only if Fosc is not an exact multiple of the desired baud rate.

Using the internal RC oscillator (4 MHz) *can* result significant rounding
error at high baud rates - *IF* you are using standard baud rates.  For PIC
to PIC communications, one can choose a non-standard baud rate with no
rounding error at the desired speed.

However, having said all that, I feel that using the internal RC oscillator
for the timebase for serial comms is iffy at best.  I don't use it in my
products - I have to operate over the temperature range of -40 through +85C
in almost everything I ship.  The internal RC oscillator just isn't stable
enough over that wide a temperature range.

One can design a serial protocol that adjusts to the correct baud rate
automatically.  This involves measuring the width of one or more bits in
terms of the number of clock cycles, then adjusting the sample delays or,
in the case of hardware UART, adjusting the baud rate registers.  But this
requires designing an appropriate protocol from the ground up.  Again - so
long as both ends of the link understand the requirements - no problem.

dwayne


Dwayne Reid   <@spam@dwaynerKILLspamspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
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2002\02\27@005430 by Byron A Jeff

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On Tue, Feb 26, 2002 at 04:23:01PM -0700, Dwayne Reid wrote:
{Quote hidden}

Now that's an explanation that I can understand. Thanks for pointing out
that the error is cumulative at any bit rate.

{Quote hidden}

What is the INTRC variability over that range?

>
> One can design a serial protocol that adjusts to the correct baud rate
> automatically.  This involves measuring the width of one or more bits in
> terms of the number of clock cycles, then adjusting the sample delays or,
> in the case of hardware UART, adjusting the baud rate registers.  But this
> requires designing an appropriate protocol from the ground up.  Again - so
> long as both ends of the link understand the requirements - no problem.

Self tracking the USART seems like a good idea.

Thanks for the heads up.

BAJ

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