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PICList Thread
'[PIC:]18F452 A2D problem'
2004\01\20@003602 by [ MTN - Harrington Street ]

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Hi
I recently started using the PIC micro (having previously used the
68HC11) mainly for hobby purposes. This week I tried to use the A2D
converter on the 18F452 and hit a problem. I initialise the A2D as
follows:

InitializeAD
       movlw   B'11111111'             ; Make PortA all  inputs
       movwf   TRISA,0
                       
       movlw   B'11000001'             ; Select RC osc, AN0 selected,
       movwf   ADCON0,0                ; A/D enabled
                       
       movlw   B'10001110'             ; Make RA0 analog input
       movwf   ADCON1,0                ;Use Vdd and Vss as reference
for A2D

                                       ;Not using interrupts(polling
GO/DONE bit)
       return        

In this configuration, the A2D result reads full scale (3F) when the
input voltage is only about 3.52V. I first had a MPX5114A connected and
couldn't get anything but  '3F' so to test it I have a 5K pot connected
between 5V and ground with the wiper connected to AN0. I have a 0.1uF
cap to ground to prevent noise. If I vary the pot from 0V upwards, the
reading starts at '00' and increases till the input voltage reaches
3.52V where it reads '3F'. I tried setting the ADCON1 register so that
(PCFG0:3 = '1111') an external reference is used and physically
connected Vdd and Vss to AN3 and AN2 respectively and in this
configuration it works. I have read the documentation through a few
times and can find no reference to Vref/2 or something like that and a
friend who also uses the PIC has done the exact same thing but with a
16Fxxx chip and has no problem. Is there something that I am missing or
do I just have a defective chip (I hope not as I've used an SMD device)
I have searched the list for previous posts on this subject but haven't
found any. Please could anyone shed some light on this.
Regards
Mark
Capetown SA



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2004\01\20@022323 by Jinx

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> so to test it I have a 5K pot connected between 5V and ground

The maximum recommended pot is 2k5 for the 18F452, not 10k
as on previous families. I can't say if anything else is wrong with
your set-up but you should correct this first

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2004\01\20@040930 by hael Rigby-Jones

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>-----Original Message-----
>From: Jinx [joecolquittspamKILLspamCLEAR.NET.NZ]
>Sent: 20 January 2004 07:20
>To: .....PICLISTKILLspamspam.....MITVMA.MIT.EDU
>Subject: Re: [PIC:]18F452 A2D problem
>
>
>> so to test it I have a 5K pot connected between 5V and ground
>
>The maximum recommended pot is 2k5 for the 18F452, not 10k
>as on previous families. I can't say if anything else is wrong
>with your set-up but you should correct this first
>

A 5k pot gives a 1.25k source impedance, so this is well in spec.  A 10K pot
would be just in spec at 2.5K.

Mark, could the you post the code you are using to perform the conversion
and read the A/D result?  Is your PIC well decoupled with suitable
capacitors physically near the Vss and Vdd pins?

Regards

Mike




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2004\01\20@042837 by Jinx

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> A 5k pot gives a 1.25k source impedance

How did you arrive at that ?

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2004\01\20@043250 by Wouter van Ooijen

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> > A 5k pot gives a 1.25k source impedance
>
> How did you arrive at that ?

Highest impedance is whiper in middle position, norton (or was it
thevenin?) equivalent is to parallel both 2.5k halves for a source
impedance of 1.25k.

Wouter van Ooijen

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2004\01\20@043457 by Jinx

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> Highest impedance is whiper in middle position, norton (or was it
> thevenin?) equivalent is to parallel both 2.5k halves for a source
> impedance of 1.25k.

OK, kick ITA for me, and "wet finger mark on imaginary blackboard"
for MR-J and Wouter

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2004\01\20@055502 by [ MTN - Harrington Street ]

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>
>
>> so to test it I have a 5K pot connected between 5V and ground
>
>The maximum recommended pot is 2k5 for the 18F452, not 10k
>as on previous families. I can't say if anything else is wrong
>with your set-up but you should correct this first
>

A 5k pot gives a 1.25k source impedance, so this is well in spec.  A 10K
pot
would be just in spec at 2.5K.

Mark, could the you post the code you are using to perform the
conversion
and read the A/D result?  Is your PIC well decoupled with suitable
capacitors physically near the Vss and Vdd pins?

Hi Mike
Thanks for the reply
The board I made has the pic interfaced to a FTDI USB chip and I have
routines to send to and receive from the board and a VB6 program on my
pc to send commands and receive info and do the GUI. Both chips have a
0.1uF and 10uF tant decoupling. The whole board uses smd components with
the caps within mm of the chips.
The simple routine I use for doing the conversion is as follows:

do_b            
                       bsf     ADCON0,GO,0             ; Start  A/D
conversion
adconvtst               btfsc   ADCON0,DONE,0   ;Is conversion complete
                       goto    adconvtst               ;No, go test
again
                       
                       movf    ADRESH,w,0              ;get high byte
                       call    sendbyte                ;send it to USB                         movf    ADRESL,w,0              ;get low byte
                       call    sendbyte                ;send it to USB

                       goto    again                   ;back to read
USB for command loop




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2004\01\20@062908 by hael Rigby-Jones

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{Quote hidden}

That part looks fine.  I'm guessing you have a suitable acquisition delay
(around 15us) between setting the channel in ADCON0 and setting the GO bit?

One thing to check is that both sets of Vdd/Vss pins are definitely
connected to their respective supplies, this is just the sort of odd
behaviour that can occur if only one set of pins is powered.

Regards

Mike




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2004\01\20@064150 by [ MTN - Harrington Street ]

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> That part looks fine.  I'm guessing you have a suitable acquisition
delay >(around 15us) between setting the channel in ADCON0 and setting
the GO bit?

>One thing to check is that both sets of Vdd/Vss pins are definitely
>connected to their respective supplies, this is just the sort of odd
>behaviour that can occur if only one set of pins is powered.

At the moment I am initiating a conversion by hitting a button on the PC
and then looking at the result. The problem only occurs when I set the
A2D to use its internal Vref. If I set it to use an external Vref and
supply 5V and Gnd to the respective pins, I get the correct result.

R
Mark


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2004\01\20@071756 by Peter Onion

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> At the moment I am initiating a conversion by hitting a button on the PC
> and then looking at the result. The problem only occurs when I set the
> A2D to use its internal Vref. If I set it to use an external Vref and
> supply 5V and Gnd to the respective pins, I get the correct result.
>

I could be totally missing the point here, but looking at the data sheet
I think the internal reference in only 3v ?  So inputs greater than this
give f.s.d. (0x3f) I think.

(Flame suit on)  ;-)

Peter



> R
> Mark
>
>
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2004\01\20@073246 by Olin Lathrop

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Mark Beetge [ MTN - Harrington Street ] wrote:
> In this configuration, the A2D result reads full scale (3F) when the
> input voltage is only about 3.52V.

3Fh is never full scale no matter how you set up the A/D.  The 18F452 has a
10 bit A/D, the result of which can be either right or left justified into a
16 bit integer.  Full scale is therefore either 3FFh or FFC0h.


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2004\01\20@073701 by Olin Lathrop

face picon face
Jinx wrote:
>> so to test it I have a 5K pot connected between 5V and ground
>
> The maximum recommended pot is 2k5 for the 18F452, not 10k
> as on previous families. I can't say if anything else is wrong with
> your set-up but you should correct this first

The maximum recommended input impedence is 2.5Kohms.  A 5Kohm pot has its
highest impedence when the wiper is centered.  This makes a divider with two
2.5Kohm resistors, which has an impedence of 1.25Kohms.

You can use up to a 10Kohm pot.


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2004\01\20@073908 by [ MTN - Harrington Street ]

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The data sheet on page 185 indicates that the internal reference is Vdd
and Vss, but youv'e given me an idea: I use ICSP on the circuit which
means that Vdd comes via a resistor (100ohm). Tonight I will check if
maybe the voltage drop across it is too great thus giving 3.5 volts as
Vdd
Mark


> A2D to use its internal Vref. If I set it to use an external Vref and
> supply 5V and Gnd to the respective pins, I get the correct result.
>

I could be totally missing the point here, but looking at the data sheet
I think the internal reference in only 3v ?  So inputs greater than this
give f.s.d. (0x3f) I think.

(Flame suit on)  ;-)

Peter


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2004\01\20@073909 by [ MTN - Harrington Street ]

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I did send a correction email immediately after that one correcting my
typo(within 5 minutes)


-----Original Message-----
From: Olin Lathrop [olin_piclistSTOPspamspamspam_OUTEMBEDINC.COM] Sent: 20 January 2004 14:33
To: spamBeGonePICLISTSTOPspamspamEraseMEMITVMA.MIT.EDU
Subject: Re: [PIC:]18F452 A2D problem

Mark Beetge [ MTN - Harrington Street ] wrote:
> In this configuration, the A2D result reads full scale (3F) when the
> input voltage is only about 3.52V.

3Fh is never full scale no matter how you set up the A/D.  The 18F452
has a
10 bit A/D, the result of which can be either right or left justified
into a
16 bit integer.  Full scale is therefore either 3FFh or FFC0h.


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(978) 742-9014, http://www.embedinc.com

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2004\01\20@074529 by hael Rigby-Jones

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{Quote hidden}

There is no internal reference per se.  The A/D converter either uses the
supply rails as the reference, or external voltages applied to the Vref+ and
Vref- pins.

Regards

Mike




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2004\01\20@074737 by Olin Lathrop

face picon face
Mark Beetge [ MTN - Harrington Street ] wrote:
> The problem only occurs when I set the
> A2D to use its internal Vref. If I set it to use an external Vref and
> supply 5V and Gnd to the respective pins, I get the correct result.

Are all the other PIC pins between 0 and 5V?  I've seen strange things
happen to A/D readings when even a little current goes thru a protection
diode, particularly if it's another analog input.


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2004\01\20@075359 by Olin Lathrop

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Mark Beetge [ MTN - Harrington Street ] wrote:
> I did send a correction email immediately after that one correcting my
> typo(within 5 minutes)

Which I saw after sending my response to your first post, of course.

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2004\01\20@080229 by Peter Onion

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On Tue, 2004-01-20 at 12:32, Mark Beetge [ MTN - Harrington Street ]
wrote:
> The data sheet on page 185 indicates that the internal reference is Vdd
> and Vss, but youv'e given me an idea: I use ICSP on the circuit which
> means that Vdd comes via a resistor (100ohm). Tonight I will check if
> maybe the voltage drop across it is too great thus giving 3.5 volts as
> Vdd
> Mark
I was looking at Page 289 of 39564b, table 22-21, but I think I
mis-understood what it means by "vref"  ... D'OH !

Peter

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2004\01\20@080437 by Peter Onion

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On Tue, 2004-01-20 at 12:43, Michael Rigby-Jones wrote:

> >Peter
>
> There is no internal reference per se.  The A/D converter either uses the
> supply rails as the reference, or external voltages applied to the Vref+ and
> Vref- pins.

Yes I see that now, I was misunderstanding the figure given
for the minimum difference between the two reference voltages.

Sorry !

D'OH !

Peter

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2004\01\20@092316 by

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Peter Onion wrote :

> I could be totally missing the point here, but looking at the
> data sheet I think the internal reference in only 3v ?  So
> inputs greater than this give f.s.d. (0x3f) I think.


I don't think there even *is* an internal V-ref for the ADC.
It can use Vdd or an *external* V-ref.

Are you sure you aren't thinking of the V-ref for the LVD ?

Jan-Erik.

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2004\01\20@100707 by Roy J. Gromlich

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Jan-Erik Soderholm:
I believe you are correct - as far as I can tell from the docs (DS39564A page 181) the A/D uses either an external Vref or the Vdd / Vss voltage. The Block Diagram on this page clearly shows this connection via PCFG0.

Unless the input pin is not correctly defined as ANALOG IN in the config. register, I can't see any reason for full scale being other than Vdd.  I just tried the experiment on my test card and I do read $3ff for an input from Vdd.

Roy J. Gromlich

Jan-Erik Soderholm XA (TN/PAC) <TakeThisOuTjan-erik.xa.soderholmspamspamERICSSON.COM> wrote :

{Quote hidden}

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2004\01\21@003343 by [ MTN - Harrington Street ]

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Found the problem, the voltdrop across the 100ohm series resistor I use
with the ICSP caused the problem. I've shorted it out but now I have to
unplug the USB cable every time I program it so as not to have power go
back into the PC and then unplug the programmer every time I connect the
circuit to the PC (Using power from the pc USB ) Has anyone got any
suggestions as to how to get around this inconvenience?
Thanks to all for their input.
Regards
Mark

{Original Message removed}

2004\01\21@144202 by Richard.Prosser
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face
How about series diodes in the power supplies ? 0.6V drop may be OK (or
less if you use schottys)
Or run off the USB supply only?
RP


Found the problem, the voltdrop across the 100ohm series resistor I use
with the ICSP caused the problem. I've shorted it out but now I have to
unplug the USB cable every time I program it so as not to have power go
back into the PC and then unplug the programmer every time I connect the
circuit to the PC (Using power from the pc USB ) Has anyone got any
suggestions as to how to get around this inconvenience?
Thanks to all for their input.
Regards
Mark

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2004\01\23@104827 by Roy J. Gromlich

picon face
-- Original Message --
From: Jinx <EraseMEjoecolquittspam@spam@CLEAR.NET.NZ>
THe bottom of the 5K pot is connected to circuit Ground.
The top is connected to some voltage source, which is considered to be a Low impedance (if it IS a voltage source).  The pot wiper is centered.  
Now assume you are the A/D input looking OUT toward the pot.
You see 2.5K to Ground (bottom half) and 2.5K to the Voltage Source (top half).
Because the V.S. (top) is Low-Z it can also be considered to be connected to ground (from the viewpoint of the A/D input).

So you have 2.5K in parallel with 2.5K = 1.25K.


To: @spam@PICLISTspam_OUTspam.....MITVMA.MIT.EDU
Send: 2004-01-20
Subject: Re: [PIC:]18F452 A2D problem

&gt; A 5k pot gives a 1.25k source impedance

How did you arrive at that ?

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2004\01\23@111908 by Spehro Pefhany

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At 09:53 AM 1/23/2004 -0500, you wrote:
>-- Original Message --
>From: Jinx <joecolquittspamBeGonespamCLEAR.NET.NZ>
>THe bottom of the 5K pot is connected to circuit Ground.
>The top is connected to some voltage source, which is considered to be a =
>Low impedance (if it IS a voltage source). =20
>The pot wiper is centered. =20
>
>Now assume you are the A/D input looking OUT toward the pot.
>You see 2.5K to Ground (bottom half) and 2.5K to the Voltage Source (top =
>half).
>Because the V.S. (top) is Low-Z it can also be considered to be connected=
>  to ground (from the viewpoint of the A/D input).
>
>So you have 2.5K in parallel with 2.5K =3D 1.25K.


This assumes that the voltage source (Vdd, below) is regulated. If the
voltage on the pot is established by a voltage divider it's a bit more
complex (see below). For the situation Roy describes:

                                     Vdd
                 Vdd                  o
                  o                   |
                  |                  .-.
                 .-.                 | |  R*(1-a)
   Rotation 0..1 | |<--o             | |
                 | |                 '-'
               R '-'                  |
                  |                   +-------o
                  o                   |
                  0V                 .-.
                                     | | R*a
                                     | |
                                     '-'
                                      |
                                      o
                                      0V


Note that the impedance for R=5K varies from 0 to 1.25K (ideal pot),
with the maximum when the wiper is centered.

Rp = a*R || (1-a)*R  where R is the element resistance, a is the
shaft electrical rotation from 0..1

  = R * (a - a^2)

You can find the min/max by setting dRp/da = 0, so

0 = 1 - 2*a => a = 0.50.

If the voltage on the pot is established by a voltage divider
the maximum impedance will always be higher, and the maximum will occur
at a pot rotation closer to maximum rotation. Limiting case (a current source)
will give an impedance maximum of R, not R/4, occurring at the maximum
position of the pot rotation, not halfway. Or, suppose we have a 5K
pot with 5K in series from the top to Vdd (bad design, but let that slide..)
Then the maximum will occur at 100% rotation (as it will for any series
resistance >= R) and will be Rp = 2.5K.

Or if there was 1K in series with the top of the element, the maximum would
occur
at 0.60 rotation and would be 1.5K. Etc.

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
RemoveMEspeff@spam@spamspamBeGoneinterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

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2004\01\23@160155 by Jinx

face picon face
Thanks for the calcs Spehro. That's helpful to know. For example
I have a circuit that uses 1k pots on 452 ADC channels. Now I know
that I could actually use anything up to 10k, and can calculate the
impedance if they were powered via a divider (from before the
regulator for instance)

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