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'[PIC:] LV ICSP programming'
2002\07\30@161934 by Harold M Hallikainen

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I'm looking at moving a project from the 18f452 to the 18fxx20 to get
more I/O and ROM space. I'm also looking at using ICSP with this part.
The Microchip application notes on low voltage ICSP seem a bit sketchy.
However, it LOOKS like LVICSP uses RB5 as a program enable (to be held
low during normal operation), RB6 as a clock line, and RB7 as a
bidirectional data line. It SEEMS that these three lines could be driven
by a PC parallel port, making a "software only" programmer. Does anything
like this exist?

Thanks!

Harold



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2002\07\31@041521 by Wouter van Ooijen

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> However, it LOOKS like LVICSP uses RB5 as a program enable (to be held
> low during normal operation), RB6 as a clock line, and RB7 as a
> bidirectional data line. It SEEMS that these three lines
> could be driven by a PC parallel port, making a "software only"
programmer.

Not reliably because a lot of parallel ports output only a weak 3.3 Volt
when high. Hence the need for a buffer chip.

Wouter van Ooijen

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2002\07\31@051220 by Roman Black

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face
Wouter van Ooijen wrote:
>
> > However, it LOOKS like LVICSP uses RB5 as a program enable (to be held
> > low during normal operation), RB6 as a clock line, and RB7 as a
> > bidirectional data line. It SEEMS that these three lines
> > could be driven by a PC parallel port, making a "software only"
> programmer.
>
> Not reliably because a lot of parallel ports output only a weak 3.3 Volt
> when high. Hence the need for a buffer chip.


I'm curious why? The parallel port and the 3.3v high
level are all typical for TTL logic. Are you saying
the PIC inputs are not compatible with standard TTL
logic high/low levels?

AFAIK the parallel ports are not good enough to be
used as 5v supply pins, but ARE perfectly acceptable
as digital outputs.
-Roman

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2002\07\31@064214 by Alain Pelletier

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I'm using this setup without buffer and it works well.  The pins have a low
output voltage but remember that there is a shmitt trigger at the input of
the pics.

keep your wires short 60 cm - 2' and remember that it may not work

Alain

{Original Message removed}

2002\07\31@083138 by Byron A Jeff

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On Tue, Jul 30, 2002 at 01:16:13PM -0700, Harold M Hallikainen wrote:
> I'm looking at moving a project from the 18f452 to the 18fxx20 to get
> more I/O and ROM space. I'm also looking at using ICSP with this part.
> The Microchip application notes on low voltage ICSP seem a bit sketchy.
> However, it LOOKS like LVICSP uses RB5 as a program enable (to be held
> low during normal operation), RB6 as a clock line, and RB7 as a
> bidirectional data line. It SEEMS that these three lines could be driven
> by a PC parallel port, making a "software only" programmer. Does anything
> like this exist?

Of course. Other than the location of PGM on RB5, my Trivial LVP programmer
will do fine programming the 18FXXX parts.

But go and take a look at my TLVP page for a discussion of the issues of the
modern PC parallel port. Also you can review the thread that Brendan and I
have had with the 'THVP'. My page:

http://www.finitesite.com/d3jsys

The failure is software. The programming algorithm is completely different
than the 16FXXX series. Personally I plan the same gameplan as I have for the
16F87X parts: simple hardware programmer to dump a bootloader, then use the
bootloader forever more to program the part.

I think it'll take another 6 months or so for the 18F series to really get
rolling...

BAJ

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2002\07\31@085119 by Byron A Jeff

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On Wed, Jul 31, 2002 at 07:08:13PM +1000, Roman Black wrote:
> Wouter van Ooijen wrote:
> >
> > > However, it LOOKS like LVICSP uses RB5 as a program enable (to be held
> > > low during normal operation), RB6 as a clock line, and RB7 as a
> > > bidirectional data line. It SEEMS that these three lines
> > > could be driven by a PC parallel port, making a "software only"
> > programmer.
> >
> > Not reliably because a lot of parallel ports output only a weak 3.3 Volt
> > when high. Hence the need for a buffer chip.
>
>
> I'm curious why? The parallel port and the 3.3v high
> level are all typical for TTL logic. Are you saying
> the PIC inputs are not compatible with standard TTL
> logic high/low levels?

Correct. They are compatible with the standard CMOS inputs. High has always
been specified as 0.8Vdd. So the standard voltage required is 4.0 volts.

I just took a quick perusal of the 18FXXX's and the 16F87X datasheets. Roman
is correct that they are specified as TTL input. But get this: in programming
mode they switch to Schmitt Trigger inputs! As such they are specified again
as the 0.8Vdd for high.

Ny solution, which Brendan seems to think is unique, is to use a HCT buffer
inbetween the port and the part. The buffer converts the TTL compatible inputs
into CMOS compatible inputs.

Another possibility which another one of my users found to work is to use a
74HC14 Schmitt Trigger Inverter. According to the Fairchild datasheet it'll
switch over at less than 3V for a 5V supply and will give sharp clean edges
at CMOS levels.

>
> AFAIK the parallel ports are not good enough to be
> used as 5v supply pins,

Correct. I steal power from the joystick port, the keyboard port, and trying
to figure out how to steal from the USB port.

> but ARE perfectly acceptable as digital outputs.

Nope. During the course of support my TLVP, it is clear that there must be
at minimum a pullup resistor involved, and a buffer perferably for reliable
operation.

BAJ

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2002\07\31@141041 by Dwayne Reid

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At 07:08 PM 7/31/02 +1000, Roman Black wrote:

>I'm curious why? The parallel port and the 3.3v high
>level are all typical for TTL logic. Are you saying
>the PIC inputs are not compatible with standard TTL
>logic high/low levels?

Because those pins have schmitt trigger input stages when used for
programming.  I think that the input thresholds are 15% & 85% of the Pic's
Vdd supply (warning: from memory - check the data sheet!).  So, no.  The
pins are *not* TTL compatible when the chip is in programming mode.

dwayne

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2002\07\31@174205 by Harold M Hallikainen

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On Wed, 31 Jul 2002 08:30:35 -0400 Byron A Jeff <byronspamKILLspamCC.GATECH.EDU>
writes:
>
> I think it'll take another 6 months or so for the 18F series to
> really get
> rolling...
>

       We're now using the 18F452 in several products in production. I'll have
a look at your page on using the LV ICSP.

Thanks!

Harold




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2002\07\31@174211 by Harold M Hallikainen

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On Wed, 31 Jul 2002 07:36:29 -0300 Alain Pelletier <.....alainKILLspamspam.....NIKDESIGN.COM>
writes:
> I'm using this setup without buffer and it works well.  The pins have
> a low
> output voltage but remember that there is a shmitt trigger at the
> input of
> the pics.
>
> keep your wires short 60 cm - 2' and remember that it may not work
>

       Are you doing the LV ICSP with an LPT port? What software are you using?

Harold

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2002\07\31@174222 by Harold M Hallikainen

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On Wed, 31 Jul 2002 09:35:09 +0200 Wouter van Ooijen <EraseMEwfspam_OUTspamTakeThisOuTXS4ALL.NL>
writes:
> > However, it LOOKS like LVICSP uses RB5 as a program enable (to be
> held
> > low during normal operation), RB6 as a clock line, and RB7 as a
> > bidirectional data line. It SEEMS that these three lines
> > could be driven by a PC parallel port, making a "software only"
> programmer.
>
> Not reliably because a lot of parallel ports output only a weak 3.3
> Volt
> when high. Hence the need for a buffer chip.
>

       Looking at the PIC18fxx20 datasheet, we see that the portB pins going to
the LV ICSP circuitry have schmitt trigger inputs. These require 0.8Vcc
for a 1, so 3.3V is indeed not enough. Seems like something with pull-up
resistors on the parallel port could solve the problem. Does software
exist that would drive the LPT lines for this purpose from MPLAB?

Harold

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