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'[PIC:] How fast can the B0 interupt occur'
2004\04\22@112921 by Jamie Jensen

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Pondering.....how fast of a signal can cause the B0 interupt to occur.  I assume, as fast as you can enter the ISR, process the code for the interupt, clear the bit and return....you can enter it again.

I also assume, if you clear the bit first thing, and another interupt occurs while processing the ISR, it will force you right back to the ISR as soon as you return.

correct assumptions?

jj


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2004\04\22@113538 by hael Rigby-Jones

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>-----Original Message-----
>From: Jamie Jensen [spam_OUTj_j_140909TakeThisOuTspamYAHOO.COM]
>Sent: 22 April 2004 16:30
>To: .....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU
>Subject: [PIC:] How fast can the B0 interupt occur
>
>
>Pondering.....how fast of a signal can cause the B0 interupt
>to occur.  I assume, as fast as you can enter the ISR, process
>the code for the interupt, clear the bit and return....you can
>enter it again.
>
>I also assume, if you clear the bit first thing, and another
>interupt occurs while processing the ISR, it will force you
>right back to the ISR as soon as you return.
>
>correct assumptions?
>
>jj

Yes!

Regards

Mike




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2004\04\22@114746 by Bob Ammerman

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----- Original Message -----
From: "Jamie Jensen" <.....j_j_140909KILLspamspam.....YAHOO.COM>
To: <EraseMEPICLISTspam_OUTspamTakeThisOuTMITVMA.MIT.EDU>
Sent: Thursday, April 22, 2004 11:30 AM
Subject: [PIC:] How fast can the B0 interupt occur


> Pondering.....how fast of a signal can cause the B0 interupt to occur.  I
assume, as fast as you can enter the ISR, process the code for the interupt,
clear the bit and return....you can enter it again.

Yes

> I also assume, if you clear the bit first thing, and another interupt
occurs while processing the ISR, it will force you right back to the ISR as
soon as you return.

Yes

To understand what is going on under the hood:

Remember the INT signal is edge triggered. Basically the B0 pin is connected
(possibly thru an inverter depending on which edge you are interested in) to
the clock input of a D flip-flop. The D input is connected to a constant HI
signal. The Q output of the flip-flop is the INTF interrupt flag. Clearing
INTF actually resets the flip-flop. This means that any (positive/negative)
edge that occurs after you clear INTF will result in setting INTF again.
Things are somewhat complicated by a stage or two of logic that synchronizes
the B0 input with the system clock to avoid metastable conditions, but this
can generally be ignored.

Bob Ammerman
RAm Systems

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