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'[OT] Lattice Synario and GALs question'
1998\07\07@092824 by Pavel Korensky

flavicon
face
Dear friends,

one or two weeks ago, I posted in the PIC list some questions regarding the
GAL/PAL programmer. One of the answers was about the Lattice ispGALs and
about the free Synario package for custom ICs development.
I tried this possibility and IT WORKS :-))

I bought several ispLSI1016 and 1032 chips from Lattice distributor,
downloaded the Synario package, built the isp programming cable. I started
to learn the package last week and during the weekend, I succesfully built
my first custom IC. It is the three channel stepper motor driver (three
step/dir ports, half/full step, outputs for three bipolar stepper motors
with modified half step). Very nice, works like a charm in test circuit :-))

But I have one question. Can anybody who is using this package tell me, how
I can use the macros which are included in /MACROS directory ? These files
has the extension .lat, but I am not able to use them neither in Abel-HDL
language, nor in the schematic entry. It is a pitty, because there is a lot
of nice macros inside this directory, like counters, multipliers etc.

Thank you for any answer.

PavelK

P.S. My second custom IC will be the controller for the PIC driven logic
analyser.

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1998\07\07@111615 by Mercy

flavicon
face
At 14:25 07/07/1998 +0200, you wrote:

>one or two weeks ago, I posted in the PIC list some questions regarding the
>GAL/PAL programmer. One of the answers was about the Lattice ispGALs and
>about the free Synario package for custom ICs development.
>I tried this possibility and IT WORKS :-))

Hi.
I joined the list yesterday and already got some interesting infos.
I think you are not [OT] and I am interested in FPGA and GALS as well.
What were the infos you got ? ( location of the soft ... )
Thanks in advance.

1998\07\07@125151 by Pavel Korensky

flavicon
face
At 17:12 7.7.1998 +0200, you wrote:

>Hi.
>I joined the list yesterday and already got some interesting infos.
>I think you are not [OT] and I am interested in FPGA and GALS as well.
>What were the infos you got ? ( location of the soft ... )
>Thanks in advance.
>

Look at the http://www.latticesemi.com and go to the Synario Starter Pack
page.

Bye PavelK

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1998\07\07@161917 by Leon Heller

flavicon
picon face
In message <spam_OUTm0ytWyy-00002SCTakeThisOuTspamchaos.dator3.anet.cz>, Pavel Korensky
<.....pavelkKILLspamspam@spam@DATOR3.ANET.CZ> writes
>Dear friends,
>
>one or two weeks ago, I posted in the PIC list some questions regarding the
>GAL/PAL programmer. One of the answers was about the Lattice ispGALs and
>about the free Synario package for custom ICs development.
>I tried this possibility and IT WORKS :-))
>
>I bought several ispLSI1016 and 1032 chips from Lattice distributor,
>downloaded the Synario package, built the isp programming cable. I started
>to learn the package last week and during the weekend, I succesfully built
>my first custom IC. It is the three channel stepper motor driver (three
>step/dir ports, half/full step, outputs for three bipolar stepper motors
>with modified half step). Very nice, works like a charm in test circuit :-))
>
>But I have one question. Can anybody who is using this package tell me, how
>I can use the macros which are included in /MACROS directory ? These files
>has the extension .lat, but I am not able to use them neither in Abel-HDL
>language, nor in the schematic entry. It is a pitty, because there is a lot
>of nice macros inside this directory, like counters, multipliers etc.

The macros are for use with the PDSPLUS software, not Synario. PDSPLUS
is the original "low-level" Lattice development software.

Leon
--
Leon Heller: leonspamKILLspamlfheller.demon.co.uk http://www.lfheller.demon.co.uk
Amateur Radio Callsign G1HSM    Tel: +44 (0) 118 947 1424
See http://www.lfheller.demon.co.uk/dds.htm for details of a simple AD9850
DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.

1998\07\08@095347 by Tom Handley

picon face
  Pavel, assuming you are using Synario v5.0, you need to also download
Lattice macros for v5.0. It's been awhile but there are instructions for
converting the macros for Synario. You should have an ispSyn50\generic
subdirectory. Part of the files go into a LSC subdirectory (*.sym, *.abl).
The rest go into the ispSyn50\LIB5 subdirectory (*.bl1, *.fft, etc). Make
sure you downloaded the related macro archive and check the docs. Sorry
I can't be of more help but it's been awhile... Note, I had originally
installed it from the download archives and again from the CD. Both versions
worked fine with Lattice macros but I don't recall a "macro" directory. The
related Lattice macros were installed as above in both versions.

  I've designed a PIC-based 32-bit logic analyzer that uses several Lattice
macros and 3 ispLSI1016's. I still need to finish the documentation but it's
been on hold until I catch up on other work like my garden ;-)

  - Tom

At 02:25 PM 7/7/98 +0200, Pavel Korensky wrote:
{Quote hidden}

1998\07\08@095350 by Tom Handley

picon face
  Mercy, I've added a schematic for a buffered parallel port cable and
programming board that allows you to program Lattice Semiconductor's
ispLSI1016, ispLSI2032, and ispGAL22V10 devices. This is for folks that
don't have Lattice's ISP Starter Kit. You can download the archive from my
web page at:

     http://www.teleport.com/~thandley/Wilbure.htm

  To program their ispGAL22V10 all you need is the buffered cable which
basically contains a 74HC367 and some passive components, and the ISP Daisy
Chain Download software which is also on Lattice's web site.

  For more information about Lattice Semiconductor's products and to
download the ISP Daisy Chain Download software and/or ISP Synario design
software, contact:

     http://www.latticesemi.com

  - Tom

At 05:12 PM 7/7/98 +0200, Mercy wrote:
{Quote hidden}

1998\07\08@110919 by Mercy

flavicon
face
At 06:18 08/07/1998 -0700, you wrote:
>   Mercy, I've added a schematic for a buffered parallel port cable and
>programming board that allows you to program Lattice Semiconductor's
>ispLSI1016, ispLSI2032, and ispGAL22V10 devices. This is for folks that
>don't have Lattice's ISP Starter Kit. You can download the archive from my
>web page at:

Thank you. I downloaded it and will start playing with it. I plan to use
it in a parallel port connected digital scope.
Greetings.

1998\07\08@112228 by Pavel Korensky

flavicon
face
At 06:13 8.7.1998 -0700, you wrote:
>   Pavel, assuming you are using Synario v5.0, you need to also download
>Lattice macros for v5.0. It's been awhile but there are instructions for
>converting the macros for Synario. You should have an ispSyn50\generic
>subdirectory. Part of the files go into a LSC subdirectory (*.sym, *.abl).
>The rest go into the ispSyn50\LIB5 subdirectory (*.bl1, *.fft, etc). Make
>sure you downloaded the related macro archive and check the docs. Sorry
>I can't be of more help but it's been awhile... Note, I had originally
>installed it from the download archives and again from the CD. Both versions
>worked fine with Lattice macros but I don't recall a "macro" directory. The
>related Lattice macros were installed as above in both versions.
>

Thx, I will check it.

>   I've designed a PIC-based 32-bit logic analyzer that uses several Lattice
>macros and 3 ispLSI1016's. I still need to finish the documentation but it's
>been on hold until I catch up on other work like my garden ;-)

:-)) It seems that I am trying to reinvent the wheel. Is your analyser the
commercial product or is it possible to download the schematics, firmware
etc.
I am trying to build the analyser for my own bench because all commercial
solutions are too expensive.
I downloaded the PCLA schematics (by D.L.Jones and D. Bulfoni) from web and
I started to adapt the ispLSI chips (basically trying to fit as much as
possible into one isp1032 and reduce number of ispLSI chips to one). I am
also trying to add the 16C76 control to the whole thing, mainly because I
would like to have serial communication with analyser.
If you can share the design, I can stop the effort and return to other
projects (which I should finish asap, but which are currently pushed on
stack). :-)


Best regards

PavelK

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1998\07\08@122709 by Pavel Korensky

flavicon
face
At 06:18 8.7.1998 -0700, you wrote:
>   Mercy, I've added a schematic for a buffered parallel port cable and
>programming board that allows you to program Lattice Semiconductor's
>ispLSI1016, ispLSI2032, and ispGAL22V10 devices. This is for folks that
>don't have Lattice's ISP Starter Kit. You can download the archive from my
>web page at:
>
>      http://www.teleport.com/~thandley/Wilbure.htm
>
>   To program their ispGAL22V10 all you need is the buffered cable which
>basically contains a 74HC367 and some passive components, and the ISP Daisy
>Chain Download software which is also on Lattice's web site.
>

Tom,

in your picture of the cable schematic is a small error. The cable
schematic is the same as is in the 1994 Lattice Data Book.
But it is not the same what actually is in the commercial ispDOWNLOAD cable.
There was a thread in USENET sometime ago (I found it at http://www.dejanews.com)
and someone from Lattice company posted the actual schematic of the cable.
It seems that they had some problem with the cable built around the 74HC367
chip, so they decided to remove schematic from actual databook and from Web
page.

Best regards

PavelK




P.S. Here is the above mentioned message.


========================================================================
START OF EMBEDDED MESSAGE

accordingly.  Summary:  Added 560 pF caps to ground and 100 ohm series
resistors between buffer and device.  Changed pullups to 1K.  Added 1K
pulldown to LPT pin 15 (Vcc detect).  Changed CMOS buffer to LSTTL.

Maybe when they discovered their serial connection was subject to noise,
they were too embarrassed to admit that peoples' troubles were caused by
the faulty specification and not because of poor construction.  So they
quietly upgraded their own cables and deleted the bad drawing from the
databook without providing the improved schematic.

--------------------------------------------------------------------------

  Lattice isp Cable  per p. 2-10,  1994 Lattice isp Manual
                 and per p. 2-50,  1994 Lattice Data Book
  modified per an actual cable provided in the $99 Synario ISP kit.
------------------------------------------------

  DB25 Parallel Port                            isp Interface
  ------------------                            -------------

  DY-b Pin nn                                   Label isp
   Y = I Input  Base+1:I/O Status Adr.
   Y = O Output Base+0:I/O Data Adr.
   b = bit (0 to 7) of I/O Byte
   nn = DB25S Pin Number

                              74LS367

                                Vpwr
                                _|_______
                               |    /|   |
   DI-6 Pin 10 -------------------<  |-----------SDOUT
                               |   o\|   |
                               |   |     |
                           +-------+     |
                           |   |   |     |
                           |   | |\o     |              100
   DO-0 Pin 2 -------------)-----|  >------------*---/\/\/\/---SDIN
                           |   | |/      |       |
                           +-------+     |       +-||--GND
                           |   |   |     |        560pF
                           |   | |\o     |              100
   DO-1 Pin 3 -------------)-----|  >------------*---/\/\/\/---SCLK
                           |   | |/      |       |
                           +-------+     |       +-||--GND
                           |   |   |     |        560pF
                           |   | |\o     |              100
   DO-2 Pin 4 -------------)-----|  >------------*---/\/\/\/---MODE
                    Vpwr   |   | |/      |       |
                    |      |   |   +---------+   +-||--GND
                   1K      |   |   |     |   |    560pF
                    |      |   | |\o     |   |          100    _____
   DO-3 Pin 5 ------+------+-----|  >--------)---*---/\/\/\/---ispEN
                    Vpwr       | |/      |   |   |
                    |          |   +---------+   +-||--GND
                   1K          |   |     |  _|_   560pF
                    |          | |\o     |   -
   DO-4 Pin 6 ------+------------|  >------------no connect
                               | |/      |
                               |_________|
                                      |
                                      GND
   DO-6 Pin 8 ------------+
                          | Port Sense
   DI-5 Pin 12 -----------+

                                           Vpwr            O Vcc
                                           |    | /|       |
   DI-3 Pin 15 ---/\/\/\/----*-------*-----*----|< |-------+
                    220      |       |          | \|
                             <     -----
                          1K <     ----- .1uF
                             |       |
   GND  Pin 20 --------------*-------*---------------------+
                                                          _|_
                                                           -

--------------------------------------------------------------------------
|
|   RJ-45 8-pin cable onto isp Starter Kit
|
|   Looking into each:                              ________
|            ________                   contacts-->|87654321|
|           |12345678|<--contacts                  |        |
|           |________|     MALE            FEMALE  |__    __|
|              (__) <---little lever               |__|__|__|
|                                        _____
|      1 - SCLK                      5 - ispEN
|      2 - GND                       6 - SDI
|      3 - MODE                      7 - SDO
|      4 - no connect                8 - Vcc
|
| |  .100" header
| |  ------------
| |  1 Vcc
| |  2 SDO
| |  3 SDI
| |  4 /ispEN
| |  5 no connect (plugged, yet wired to buffer output)
| |  6 MODE
| |  7 GROUND
| |  8 SCLK

-----------------------------------------------------------------


============================================================================
END OF EMBEDDED MESSAGE


**************************************************************************
* Pavel Korensky                                                         *
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1998\07\09@055811 by Tom Handley

picon face
  Leon, you can download the PDS macros that are compatible with Synario.
I'm using v5.0. Check their download section. I had started with PDS around
three years ago so fortunately I have the book covering the macros. I've
found the converted Synario macros work as the book describes. Note, not all
of the PDS macros are available. They do include the counters, shift
registers, mux/demux's, and comparators.

  I also noticed a newer archive with converted macros for Synario v5.1. I
assume the on-line version has been updated but I have'nt had time to check
it out.

  - Tom

At 09:17 PM 7/7/98 +0100, Leon Heller wrote:
>In message <.....m0ytWyy-00002SCKILLspamspam.....chaos.dator3.anet.cz>, Pavel Korensky
><EraseMEpavelkspam_OUTspamTakeThisOuTDATOR3.ANET.CZ> writes
>>Dear friends,
[snip]
{Quote hidden}

1998\07\09@083555 by Tom Handley

picon face
  Mercy, Pavel pointed out that Lattice switched to a 74LS367 and the two
10K pullups were changed to 1K. Other than that, the interface is fine. I
would socket the 74xx367 and go ahead and use 1K pullups on the 74xx367 pins
12 and 14. Note, the schematic I posted is from the commercial ISP cable
that came with the ISP Starter Kit that I bought around 3 years ago and I've
never had any problems. As with anything connected to the parallel port,
it's very important to have a good ground from the port to your interface.

  - Tom

At 04:15 PM 7/8/98 +0200, Mercy wrote:
{Quote hidden}

1998\07\09@083605 by Tom Handley

picon face
  Pavel, my goal is to provide the core logic and supporting hardware
design for the logic analyzer. Then I want to release it to the public in
hopes that the software becomes a group effort. While I want this to be a
PIC project I'm also designing it to be compatible with a PC host using a
parallel port. I am also looking at using a 16C76 or 16C77. The host
interface requires 15 I/Os in the 4-Bit transfer mode and 19 in the 8-Bit
mode. One issue is the time it takes to transfer up to 128KBytes of data
to a PC for each sample.

  If you are using the ispLSI1032, then you must have the full version of
the Lattice fitter and Synario. I only have the starter kit. It would cost
around $2500+ to upgrade. It's hard to justify the expense for a
vendor-specific product line even though Lattice is local here in Portland
and I've been using their products for around three years. I could easily
put this in a 1032... The design could still be shared as the Daisy Chain
Download Software is free. I'm providing the JEDEC and ISP Stream files in
addition to the schematics. Note, I'm avoiding getting specific in certain
aspects of the schematics such as the pod buffers as there are a lot of ways
to do this and I want to leave that up to the users.

  I had to `jump through many hoops' to fit as much as I did into three
ispLSI1016's. If I went to a 1032, I would start over taking the custom
modules that I designed and providing better integration. For example, a lot
of the configuration is handled by an SPI-style serial interface with shift
registers in all three chips. So two chips have SDI, SDO, and SCLK lines
while the remaining chip has SDI and SCLK inputs... Several shift register
outputs use external pins to connect to the other chips. Still, it replaces
dozens of 74xx `glue' logic...

  As far as testing, I only have the functional waveform test in Synario.
The Timing Analyzer is only included in the full version. I've ran
functional tests on the ABEL modules and the top-level schematics as well as
static tests on the chips. That's a long ways from the `real-world' though.
I'll probably release the preliminary design before I actually build my own
prototype.

  - Tom

At 05:08 PM 7/8/98 +0200, Pavel Korensky wrote:
>At 06:13 8.7.1998 -0700, Tom Handley wrote:
[snip]
{Quote hidden}

1998\07\09@083611 by Tom Handley

picon face
  Pavel, thanks! Note, I was working from the Lattice data book and the
commercial cable that I use from the ISP Starter Kit that I bought around
three years ago. I noticed a discrepancy between the two and generated the
schematic based on my cable as well as the prototype programming board that
I use. I have never had any problems programming ispLSI1016s, 2032s, and
GAL22V10s. Given the noise immunity of the 74HC family I'm curious as to why
they would go back to the 74LS part. I can only speculate that they had
drive problems relating to driving several daisy-chained devices or the
newer 1016E. I'll update my schematic to provide 1K pullups instead of 10K
but I should give Lattice a call to see why they changed the 74xx367. The
other updates are already included in my schematic.

  - Tom

At 05:20 PM 7/8/98 +0200, Pavel Korensky wrote:
{Quote hidden}

1998\07\09@125135 by Pavel Korensky

flavicon
face
At 05:31 9.7.1998 -0700, you wrote:
>   Pavel, my goal is to provide the core logic and supporting hardware
>design for the logic analyzer. Then I want to release it to the public in
>hopes that the software becomes a group effort. While I want this to be a
>PIC project I'm also designing it to be compatible with a PC host using a
>parallel port. I am also looking at using a 16C76 or 16C77. The host
>interface requires 15 I/Os in the 4-Bit transfer mode and 19 in the 8-Bit
>mode. One issue is the time it takes to transfer up to 128KBytes of data
>to a PC for each sample.
>

You are right, the speed of transfer is a problem. But also a problem is,
that PCs in a lot of personal workshops have parallel port occupied by PIC
or EPROM programmer, printer, hardware keys for development system (like
OrCAD) etc. We need more parallel ports in PC :-))
So, I tought that serial port can be better. With 38400 bps serial port,
the whole transfer will be around 35 seconds. It is annoying I know, but
half minute is not so much, because examining the results will take much
more time. The second main reason for serial port is, that programs which
are using serial port can run on WinNT without any problem. Yes, I know
that there are free programs for accessing the parallel port under WinNT,
but it is necessary to have two versions of PC software.
But maybe I am wrong.

>   If you are using the ispLSI1032, then you must have the full version of
>the Lattice fitter and Synario. I only have the starter kit. It would cost
>around $2500+ to upgrade. It's hard to justify the expense for a

>vendor-specific product line even though Lattice is local here in Portland
>and I've been using their products for around three years. I could easily

Hmm, I also have the Synario Starter and it can use 1032 parts. I tried it
(simulation of course) and it works, no problems with using 1032. I thought
that Synario starter can be used up to 6000 gates, which is OK for 1032.
But I will check it once more. You scared me, because I ordered several
1032 chips yesterday.

>I'll probably release the preliminary design before I actually build my own
>prototype.

It will be nice. Thank you in advance.

Best regards

PavelK

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1998\07\09@125618 by Pavel Korensky

flavicon
face
At 05:31 9.7.1998 -0700, you wrote:
>   As far as testing, I only have the functional waveform test in Synario.
>The Timing Analyzer is only included in the full version. I've ran
>functional tests on the ABEL modules and the top-level schematics as well as
>static tests on the chips. That's a long ways from the `real-world' though.
>I'll probably release the preliminary design before I actually build my own
>prototype.

I just checked it on http://www.latticesemi.com. Timing Analyser is included in
Synario Starter, at least in the version which is downloadable now from the
Web. I will check it once more at home, where I have the latest downloaded
version installed.

Best regards

PavelK


Here is a quotation from the Web page:

===========================================================================

The ISP(tm) Synario Starter software is now available for download. This
software includes all the tools that you need for
designing with Lattice ispLSI(r) 1000, 1000E, 2000, 2000V, and GAL(r)
device families. The ISP Synario Starter runs
under Windows NT(r) and Windows 95(r), and includes:

   Lattice ispDS+(tm) Starter (Part 1)
       ispDS+ HDL Synthesis-Optimized Logic Fitter
       Explore Tool
       Pin Assignment Editor
       ispTA(tm) Timing Analyzer
       ispDOWNLOAD(tm) and ispATE(tm) Utilities
       VITAL and Non-VITAL VHDL Simulation Libraries
       OVI-Compliant Verilog Simulation Library

   ISP Synario Software Starter (Part 2)
       ISP Synario Project Navigator GUI
       ISP Synario ABEL-HDL Entry and Compiler
       ISP Synario Functional Simulator
       ISP Synario Schematic Capture
       GAL Compiler

Download the ISP Synario Starter today, and join the ISP revolution!

========================================================================

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1998\07\09@235316 by Leon Heller

flavicon
picon face
In message <1.5.4.32.19980709123128.0066ec5cspamspam_OUTmail.teleport.com>, Tom
Handley <@spam@thandleyKILLspamspamTELEPORT.COM> writes
>   Pavel, my goal is to provide the core logic and supporting hardware
>design for the logic analyzer. Then I want to release it to the public in
>hopes that the software becomes a group effort. While I want this to be a
>PIC project I'm also designing it to be compatible with a PC host using a
>parallel port. I am also looking at using a 16C76 or 16C77. The host
>interface requires 15 I/Os in the 4-Bit transfer mode and 19 in the 8-Bit
>mode. One issue is the time it takes to transfer up to 128KBytes of data
>to a PC for each sample.
>
>   If you are using the ispLSI1032, then you must have the full version of
>the Lattice fitter and Synario. I only have the starter kit. It would cost
>around $2500+ to upgrade. It's hard to justify the expense for a
>vendor-specific product line even though Lattice is local here in Portland
>and I've been using their products for around three years. I could easily
>put this in a 1032...

[deleted]

The current Lattice starter software available for downloading from
their web site will program all their 1000 and 2000 series devices,
including the 1032 - up to 8000 gates.

Leon
--
Leon Heller: KILLspamleonKILLspamspamlfheller.demon.co.uk http://www.lfheller.demon.co.uk
Amateur Radio Callsign G1HSM    Tel: +44 (0) 118 947 1424
See http://www.lfheller.demon.co.uk/dds.htm for details of a simple AD9850
DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.

1998\07\13@133257 by Tom Handley

picon face
  Pavel, going into this I was concerned about the transfer problem whether
using a PIC or PC host. The data is still going to end up on a PC. As you
pointed out, parallel port resources are limited which is really frustrating
considering how useful that port is for hardware development and testing.
I've provided a 4-Bit transfer mode for backward-compatibility with `legacy'
parallel ports. In that mode, the CPLDs provide 4-Bit chip-selects to
74HCT244 buffers from the SRAMs. As far as a PIC and serial transfer, the
16C76/77 are an `over-kill' in this application but the BRGH `bug' is fixed
and 115.2KBaud transfer is possible with the on-board USART.

  - Tom

At 06:23 PM 7/9/98 +0200, Pavel Korensky wrote:
{Quote hidden}

1998\07\13@133304 by Tom Handley

picon face
  Pavel (And Leon), Last Friday I talked to two Lattice Engineers and
here's the deal (which you already know); Lattice is now providing, on their
web site, version 5.1 of Synario and their related fitter. It *DOES* support
the larger devices! You get a six month evaluation copy.

  As far as the download cable, they went back to a 74LS367 to support
their 3V CPLDs. I'd rather not change my schematic at this time as few folks
will use this. The 74HC367 does have better noise immunity for 5V parts and
they agreed. I will update my archive to mention the change for folks that
do use 3V logic. It would probably be best to change to 1K pullups and
socket the 74xx367.

  As far as the logic analyzer, I'm going to do a complete redesign but the
many months of effort on the original will certainly not be lost. The
capabilities and the host interface will remain. Other than the 74ACT574 pod
buffers and the SRAM, the design will be reduced to 1 CPLD instead of 3. I
can easily finish this project within the six months and Lattice folks are
glad to sell their products... End-users need only build the buffered
download cable and download the related software. I'll provide the ISP
Stream file as well as the JEDEC file for folks using commercial
programmers. Again, host software will be up to the user and I hope to see
it become a group effort.

  For the sake of the PIC archive, I'll post the current status and
detailed specs under the "PIC-based Logic Analyzer - Design update" thread.

  - Tom

At 06:43 PM 7/9/98 +0200, Pavel Korensky wrote:
{Quote hidden}

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