Post by thread:[OT] Hi-speed A/D Revisited

[spin-off from 24-bit A/D thread] In my never-ending quest to improve the ENOB [effective number of bits] in my A/D system, described in the other thread, I ran across the following datasheet, which has good info about interfacing a 42 Msps A/D, and which should be directly translatable down to slower hi-speed devices. Should be of interest to those designing similar systems. http://www.national.com/ds/AD/ADC08351.pdf There are any number of things detailed here which I probably cannot implement on my current board - due to space limitations, overall circuit complexity, etc. Some hi-lites: 1. buffer A/D data outputs to shield A/D from digital bus noise backflow. 2. [and/or] use series Rs [50-100 ohms] in lines connecting to digital cktry. 3. connect A/D digital driver supply to analog, not digital v.buss. 4. keep signal paths straight, analog drivers adjacent to A/D. 5. single-point gnd under A/D. 6. no digital lines crossing analog areas. 7. buffer clock input to A/D. 8. isolate A/D clock line from "everything" else [helps prevent cross-talk - to outbound, and jitter - from inbound]. 9. use about 6 bypass/filter caps at the A/D. 10. etc/etc. Of special note, for a number of different apps, item #2 is a very effective and simple means to isolate and protect various lines from overvoltaging, hi-speed noise, etc/etc. Small series Rs, 50-100 ohms, isolate stray capacitances and help prevent ringing on hi-speed lines. Larger series Rs, 10K range, in conjunction with either physical caps or stray capacitance and CMOS chip clamping diodes, make good low-pass filters and over- protection ckts, where you can get away with using the larger values. best regards, - Dan Michaels Oricom Technologies http://www.sni.net/~oricom ==========================