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'[OT] Clock Division (was ATMEL)'
1998\07\09@041607 by Scott Walsh

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    A few bods have mentioned that they are annoyed by the way in which a
    large number of micros divide down the external clock, resonator or
    crystal usually, and run instructions at that speed ....

    What are the reasons for people finding this so distasteful? I
    understand that clock division and PLL circuits can be noisey, but I
    get the feeling that this is not the only reason.

    regards,
    SW.


______________________________ Reply Separator _________________________________
Subject: Re: ATMEL
Author:  pic microcontroller discussion list <spam_OUTPICLISTTakeThisOuTspamMITVMA.MIT.EDU> at
INTERNET
Date:    08/07/98 12:02


It's a pity zilog hasn't seen the light. If the Z8 was flash, and didn't
have the clock/8 "feature", then they'd rule the world!

1998\07\09@095922 by Peter L. Peres

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On Thu, 9 Jul 1998, Scott Walsh wrote:

>      A few bods have mentioned that they are annoyed by the way in which a
>      large number of micros divide down the external clock, resonator or
>      crystal usually, and run instructions at that speed ....
>
>      What are the reasons for people finding this so distasteful? I
>      understand that clock division and PLL circuits can be noisey, but I
>      get the feeling that this is not the only reason.
>
>      regards,
>      SW.

The reason is, that manufacturers do not advertise MIPS, they advertise
clock frequency, so, for example, the original 8051 looked 'smashing' with
12 MHz while it was way under 1 MIPS.

It is not good for engineers to have to wade through 1/2 pound of
press releases and advertising comparisons to find out that each cycle of
that fantastic-looking 25 MHz processor takes 11 clocks, so it's really a
2.0-2.2 MIPS processor.

Next, high frequency sources contribute to power drain and to price. The
cost of a 25 MHz crystal is higher than that of a 4 MHz one. It is also
harder to make a stable oscillator at higher frequencies in a production
environment.

Nearly all systems that use a clock over 30 MHz use a 'canned' oscillator
or specially ordered resonators because of this. A replaced ceramic load
capacitor type (same spec, different supplier)  because of part supply
problems and-hop-no oscillation in 300 units or so, until someone notices
at QC and stops the pipeline. Both canned oscillators and special
resonators are expensive, and canned osciallators draw more power than a
dozen CMOS micros in parallel.

This kind of things never seem to happen under 12 MHz and above 1 MHz,
which is the range of 'best stability' crystals for the present technology
(at least it looks like that).

So, people who work with micros and have to make choices HATE this kind of
publicity and the kind of explaining they have to do to the boss and to
the client when not choosing the 'fastest' part (bosses tend not to read
about the gory small details in pamphlets ;).

In micros, MIPS/MHz and MIPS/mA count more than other considerations,
especially in high performance portable equipment. It's not like an
industrial PC where you just upgrade to 333 MHz (at a power drain of 9
Amps for the CPU alone !) only to have a CPU load of 0.1 90% of the time.

Peter

1998\07\09@113615 by STEENKAMP [M.ING E&E]

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Hi,

>      A few bods have mentioned that they are annoyed by the way in which a
>      large number of micros divide down the external clock, resonator or
>      crystal usually, and run instructions at that speed ....
>
>      What are the reasons for people finding this so distasteful? I
>      understand that clock division and PLL circuits can be noisey, but I
>      get the feeling that this is not the only reason.
>
I think one disadvantage of a clock divisor is that it limits the
maximum frequency at which a part can operate.  Take the good old 8051
for instance.  It has a /12 and therefore to have it run at an
instruction clock of 5MHz, you have to clock it at 60MHz!  Even if it
could be clocked at 60MHz, it would be a non-enjoyable execise to build a
good 60MHz oscillator and it would consume a large amount of power.

A further implication is EMC.  With EMC laws becoming stricter, it
becomes more and more important to limit the highest frequency in your
design.  If you need a 24MHz oscillator to get the same performance from
a 8051 than you would get from a 2MHz AVR (maybe even 1MHz), then the AVR
would be a far better choice on EMC considerations alone.

Just my 24/2 cents worth...
Niki

1998\07\09@121050 by 'Grif' w. keith griffith

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At 05:20 PM 7/9/98 GMT+0200, you wrote:
{Quote hidden}

I'm not at all sure on the newer processors, but from a historical
standpoint, most of the old designs needed several phases of clock for the
internal registers and so on.  Like ACC to memory buffer to memory buss to
memory, needing three phase changes just to move data from the ACC to the
memory.  I know, bad example, but the last time I really worked on anything
like that was 15 or so years ago.  The clean way, was just  a higher speed
external clock, and build your 8 phase (or whatever) sq wave from that.
I'd almost bet the current crop of micro's do the same thing internally,
depending on the design team.  After we get by the real hardware "why" of
the clock, then we can look at the marketing thing and be properly amazed
at their insights.  (cheep shot at the marketing types and the folks that
believe them).



'Grif' N7IVS

1998\07\09@125132 by David VanHorn
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>
>I'm not at all sure on the newer processors, but from a historical
>standpoint, most of the old designs needed several phases of clock for the
>internal registers and so on.  Like ACC to memory buffer to memory buss to
>memory, needing three phase changes just to move data from the ACC to the
>memory.  I know, bad example, but the last time I really worked on anything
>like that was 15 or so years ago.  The clean way, was just  a higher speed
>external clock, and build your 8 phase (or whatever) sq wave from that.
>I'd almost bet the current crop of micro's do the same thing internally,
>depending on the design team.  After we get by the real hardware "why" of
>the clock, then we can look at the marketing thing and be properly amazed
>at their insights.  (cheep shot at the marketing types and the folks that
>believe them).
>
>
>
>'Grif' N7IVS


True fact.. Some of them needed 50% duty cycle as well, and the only way to
insure that is to divide the clock once more.

When you add a few clock phases, you're up to clock/8 in no time :-P
Now your osc 3rd and 5th harmonics are up 8x higher, and it puts you
in a fair bit more trouble than you needed to be, especially if the layout
isn't spectacular.

Current draw has to be higher than it otherwise would be, which makes
more heat, EMI, and just plain costs more watts to run.

Of course bad code can also have a huge impact on the picture. I recoded
one system, and took the clock from 12.288 (which was beyond the part's
max!)
to 3.575, did the same job, and even had a little time to spare.

1998\07\09@174303 by ephen Rothlisberger

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>     A few bods have mentioned that they are annoyed by the way in which a
>     large number of micros divide down the external clock, resonator or
>     crystal usually, and run instructions at that speed ....
>
>     What are the reasons for people finding this so distasteful? I
>     understand that clock division and PLL circuits can be noisey, but I
>     get the feeling that this is not the only reason.

Annoyances:

1. Greater EM emmissions, making it harder to get FCC certification,

2. Greater power consumption, which is a problem for battery-powered devices,

3. More attention has to be given to careful oscillator design to get
accurate clocks,

4. Slower processing rates given a maximum clock speed,

and just for the principle of it,

5. The perception that all those clock cycles are being "wasted".

I designed a TI DSP-based battery-operated consumer device, and the DSP ran
at 20MIPS from a 20MHz clock, one instruction per clock cycle. This was
directly beneficial to each of the points above.

Stephen.

1998\07\10@031557 by Morgan Olsson

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>and just for the principle of it,
>
>5. The perception that all those clock cycles are being "wasted".

I think it looks the other way, since it seem crazy a simple clear
operation takes the same long time as an addition or increment.

It would make more sense if clear took 2 cycles, and addition 3 cycles,
@3MHz,
than both takong 1 cycle @1MHz.

Why should the CPU just sit and waste time waiting for next clock after
having done the clear just to make it take the same long time?

BTW, where is an ATMEL mailing list? ;)

/Morgan
/  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
\  .....mrtKILLspamspam@spam@iname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /

1998\07\10@033501 by William Chops Westfield

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Why do you think a CLEAR instruction is easier to implement that an
addition?

Most platforms that use multiple clocks per instruction have some
degree of microcoding (either actual microcode, or in hardware sortof),
and they do different parts of each operation on each cycle.  Occasionally,
the operation is regular enough that you can tell what it is doing on
each cycle...

       put the PC on the address pins.
       assert Chip select
       Read instruction
       deassert chip select
       increment PC
       set source 1 of ALU appropriately
       set source 2 of alu appropriately
       set operation of the alu
       clock alu
       store alu result in destination
       store flags
       yada, yada...


(For a good time, implement your favorite microcontroller via a paper
microcoded design.  12 clocks per instruction means 12 micro-instructions
per instruction, which sounds like a lot until you to actually do it!
Remember to strech external cycles as much as possible to allow the use of
slower memorys/etc..)

(Now, the really mind-boggling designs are the ASYNCHRONOUS (NO clock!)
designs.  I think there's a async implementation of an acorn variant..)

BillW

1998\07\10@063205 by tjaart

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N STEENKAMP [M.ING E&E] wrote:

> A further implication is EMC.  With EMC laws becoming stricter, it
> becomes more and more important to limit the highest frequency in your
> design.  If you need a 24MHz oscillator to get the same performance from
> a 8051 than you would get from a 2MHz AVR (maybe even 1MHz), then the AVR
> would be a far better choice on EMC considerations alone.

Good point. We've just gone through a few CE marking exercises, andEMC should really be in the back
of any serious engineer's mind.

> Just my 24/2 cents worth...
> Niki

Hey! If you have a look at the ZAR/USD exchange rate, you'll see
that you only had around .3125 cents worth there... :(

--
Friendly Regards

Tjaart van der Walt
tjaartspamKILLspamwasp.co.za

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1998\07\10@122946 by Morgan Olsson

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At 00:33 1998-07-10 PDT, wrote:
>Why do you think a CLEAR instruction is easier to implement that an
>addition?

Different number of microcycles are needed for different operations.

Not easier, but if effort is made on the arcietecture CLEAR do not have to
wait for fetching nothing from nowhere; 1: just set data bus Zero while
setting the register adress data bus (directly from instructions LSbits),
and 2: write!

For the single microcode for increment/decrement that operation take many
times more nanoseconds than for instance an AND, so maybe even a microcode
nop is necessary on the inc/dec to be able to not wait uselessly for the and.

Fastest is if every operation would be timed for itself, either by various
number of fast clock cycles, or some asynchronous technque.  But that is
much more design effort and hard to use for cycle timed routines.

Another issue is that the program memory must be able to fetch the next
instruction much faster for the instructio after the short-time
instruction, and also complicates the pipe-line prefetch etc.

/Morgan

/  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
\  EraseMEmrtspam_OUTspamTakeThisOuTiname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /

1998\07\13@175252 by Sean Breheny

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I really do think that you are correct. They don't simply divide the
clock by a factor and then use it, they generate several different clock
signals of different phase shifts (like quadrature, in the case of the
PIC) to synchronize various processes inside the chip. If you lok at the
pic databook, you will see that it lists what process the pic does on
each clock pulse for each instruction.

Sean

{Quote hidden}

1998\07\13@190921 by Morgan Olsson

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At 17:50 1998-07-13 -0400, you wrote:
>I really do think that you are correct. They don't simply divide the
>clock by a factor and then use it, they generate several different clock
>signals of different phase shifts (like quadrature, in the case of the
>PIC) to synchronize various processes inside the chip. If you lok at the
>pic databook, you will see that it lists what process the pic does on
>each clock pulse for each instruction.
>
>Sean

I want to add my thought about AVR timing:

I believe the AVR do about the same; but reverse: for each clock cycle it
makes intermediate states somehow internally.  Like: first, do something on
rising edge, another thing on falling edge.

If that is not enough, generate intermediate steps, and viola: we got four
steps per external clock cycle (macine cycle), like PIC got four clocks per
macine cycle!  

This intermediate step generation  might be done using simple
RC-schmidttrigger-timers, driven by the clock; as they don«t have to be
centered between the clock pulse edges, the time can be constant, but if it
is made that the times increase with higher clock cycle (pretty simple anog
design) it can work to lower supply voltage at lower clock inputs.

comments, please

/Morgan
/  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
\  mrtspamspam_OUTiname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /

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