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'[OT] 64-Kb Shift Register or Maybe a FIFO (The Aud'
2000\05\21@230824 by Martin McCormick

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       After reading all the public and private messages and
changing my mind half a dozen times, I think the best solution is
that which several suggested right off, namely a 8-kilobyte SRAM
managed by a 17C43.  The 17C43 has enough I/O lines to directly
address every line on the 6264 RAM chip plus do all the other
things I need for it to do.  It will also operate at 16.384 MHZ
which should give it enough time to handle a 64-kilobit stream as
long as the ISR is anything reasonable.  It will execute
4,196,000 normal instructions per second which should be more
than fast enough to do what needs to be done.

       I had been interested in the 64-kilobit DRAM idea until I
found out that the logic to control the addressing and
refreshment would probably be more trouble than it was worth.  My
thanks to a couple of you who pointed out what had to be done and
saved me a lot of time.

       Again, many thanks to all and it is time to get started.

Martin McCormick

2000\05\22@163654 by Marc

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>         After reading all the public and private messages and
> changing my mind half a dozen times, I think the best solution is
> that which several suggested right off, namely a 8-kilobyte SRAM
> managed by a 17C43.  The 17C43 has enough I/O lines to directly
> address every line on the 6264 RAM chip plus do all the other
> things I need for it to do.  It will also operate at 16.384 MHZ
> which should give it enough time to handle a 64-kilobit stream as
> long as the ISR is anything reasonable.  It will execute
> 4,196,000 normal instructions per second which should be more
> than fast enough to do what needs to be done.

Well when you're out for a cheaper solution, use a smaller PIC and
74HC logic instead.  One option are ser->par shift registers, another
are counters with parallel output.

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