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'[EE] scope project anyone?'
2004\09\17@111014 by Bob J

picon face
Has anyone here built one of these high storage depth DSO's?

http://www.chocbar.demon.co.uk/

It appears to be a good design, and a heck of a lot cheaper than the
pc scopes available or the old junk DSO scopes on ebay.

Regards,
Bob
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2004\09\17@162352 by Peter Johansson

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Bob J writes:

> Has anyone here built one of these high storage depth DSO's?
>
> http://www.chocbar.demon.co.uk/
>
> It appears to be a good design, and a heck of a lot cheaper than the
> pc scopes available or the old junk DSO scopes on ebay.

One interesting thing to note about this design is the date on the
accompanying paper: April 2000.  Once can assume that design concepts
were initiated at least a year prior.  At that time, the highest
speeds one could obtain without direct interfacing to the PCI bus was
12 Mbps USB, and even this may have been exotic at the time.  Instead
the design was based upon the next best thing, the PC parallel port
which tops out in the neighborhood of 500 kbps.

This is a critical issue because it requires the DSO to store and
buffer samples, and this represents the largest complexity in the
citcuit.  Four years later, with USB 2.0 and it's theoritical 480 Mbps
top end and inexpensive control circuits, the raw data stream can now
be pushed down the wire and stored on the PC.  Such a system would be
even cheaper and even easier to build than the one described above.
Sampling bandwidth would still be limited, but might be more than
enough for the casual user.

However, if internal memory would be used, it would seem to make more
sense to use it as a ring buffer to store raw data and then send a
compressed data stream down the USB wire to the PC.  This method would
allow for continuous recording at relatively high sample rates
(unless, of course, you happen to be sampling noise, but we can ignore
that for the moment...)

As some of you may remember from the "newbie pic programmer" thread I
started a week or so back, I'm recently migrating from software guy
back to a hardware guy.  As such, my test bench consists of little
more than three multi-meters.  I'm quickly finding myself in need of a
logic analyzer, o-scope, frequency generator, etc.  Unfortunately,
this is just a hobby and I cannot afford to throw lots of money into
it.

So I've been looking at the BitScope product and I'm not sure I can
determine which of the above two categories it falls into.  All of the
models seem to have an internal storage buffer (32-640 KB) and
relatively slow transfer rates (max 4 Mbits/sec) and it is unclear to
me whether they simply buffer a small sample and upload it to the PC,
or whether they use the buffer as temporary storage for raw data and
then send a continuous compressed data stream up to the PC.

Then there is the USBee which definitely streams raw data to the PC,
but this device is simply analog and doesn't include the o-scope.

Decisions, decisions!

I've also been toying with the idea of building my own since I don't
need high-frequency sampling rates right now, and might not need them
any time soon.  In fact, it looks as if a *very* simple circuit using
the USB 1.1 based Elexol USB MOD2 ($30) combined with an SX running at
50 Mhz will provide me with adequate sampling rates.  Unfortunately,
similar USB 2.0 kits run upwards of $150, so this isn't quite cost
effective right now, but I'd be willing to bet that we'll see a good
price drop in the next year or so.

As an aside, for my immediate usage I do *not* need a GUI-based
display, as all of my signal analysis will be performed by custom C
code on the resulting data files.  The real benefit of the prebuilt
systems like the USBee and the BitScope are not so much in the
hardware but rather the software at the PC end...

-p.
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2004\09\17@184239 by David P Harris

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No, but I have thought about it :-)
We would need to have some boards made, I think.
I would like to collaborate, if people are interested.
David


Bob J wrote:

{Quote hidden}

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2004\09\17@190752 by Alexandre Guimaraes

face picon face
   I have a old Bitscope and find it quite disapointing some times. I also
have a Gagescope and that is really nice to use. But... I am looking for
something that could be plugged on the notebook and walk around with me
sometimes...

   If we can get a group of people interested I can draw the boards and
make the first prototype to get the hardware working... I can make some more
boards to interested people at the cost. I am not sure how cheap it would be
as I am down in Brazil. I would go for a design with mixed 0805 SMD's and
trough hole for the harder to get parts.

   We would need more people for the hardware design and software on the PC
and also someone that is willing to take the project leader place. Without a
leader with "absolute" powers the cooperative effort usually does not get
anywhere.

   I would be quite satisfied with something that can sample at around 200
khz. I almost never use the clock on my gagescope faster than that for
microcontroller or analog projects. It might really be possible to do the
aquisiction on a microcontroller board and send all the raw data to a PC to
make all the processing. 12 Bits would probably be still pretty cheap bellow
1 msps.

best regards,
Alexandre Guimaraes


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2004\09\17@193831 by Marc Nicholas

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It's definitely a neat project.

Couple of comments:

- I think the FLEX 8K is EOL'd?
- Parallel interface isn't applicable to today's needs or personal
computing environments. I'd be game for implementing USB1.0 at the very
least. (We can do both the PHY and MAC in a entry-level FPGA...USB 2.x
would likely require the PHY as an ASIC).
- USB might (haven't done the napkin-work) relieve the need to use much in
the way of local storage. If not, probably easy/quick to use ZBT SRAM.
- I'm horrible for PCB work...I could do the FPGA stuff with effort ;-)

There are enough interesting/capable/dedicated people here to produce
something rivalling a commercial product. I actually really, REALLY need a
decent multi-channel logic analyzer right now, so would be prepared to
invest some sweat equity.

Comments?

-marc

On Fri, 17 Sep 2004, David P Harris wrote:

{Quote hidden}

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2004\09\17@194446 by Marc Nicholas

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Did you just say you'd do boards? :-)

I've been preaching a bit about FPGAs the past couple of days (sorry). You
need the speed and predictability (important) of a hardware-oriented
solution here. I just can't see the use of a PIC here anywhere (and am
glad this is under [EE]: because of that).

I also firmly believe a device such as this must be multifunction. A pure
DSO is unlikely to excite folk. A 16+ channel logic analyzer is a nice
adjunct. And stuff like function generators become pretty easy once the
former are done.

If can model this around Altera's Cyclone, I have enough hardware here
right now to start doing the FPGA stuff. The Cyclone is also cheap, has
memory interface glue and IP for free, and has a sister PROM for
programming on startup.

-marc

On Fri, 17 Sep 2004, Alexandre Guimaraes wrote:

{Quote hidden}

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2004\09\17@195311 by Shawn Wilton

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I don't think it would be wise to remove the local storage.  You're
going to want that storage to maintain a high sampling rate.

-Shawn


Marc Nicholas wrote:
{Quote hidden}

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2004\09\17@203505 by Marc Nicholas

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I really meant *additional* local storage....we can build a nice buffer in
FPGA.

-marx

On Fri, 17 Sep 2004, Shawn Wilton wrote:

{Quote hidden}

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2004\09\17@204354 by Alexandre Guimaraes

face picon face
Hi, Marc

> Did you just say you'd do boards? :-)

   I can draw the boards, spend some money to make the prototype and I can
make more boards to anyone participating at the project just for the cost of
the boards as they come from the board house. I will pay for the films and
startup fees myself. I am not sure how cheap I pay for boards when compared
to Olimex or other board houses but I can get gerbers available to anyone
and each person can use whatever board house. The main advantage is that I
will have the design debugged before other people need to invest money on
it... Besides as I am down in Brazil I will also need some help to buy the
parts and we can trade :-)

> I've been preaching a bit about FPGAs the past couple of days (sorry). You
> need the speed and predictability (important) of a hardware-oriented
> solution here. I just can't see the use of a PIC here anywhere (and am
> glad this is under [EE]: because of that).

   It may be easier to use a microcontroller, specially to make the
interface to the PC easier. The trigger has to be on the FPGA for sure... Or
if we go with low speed everything can be in the microcontroller. Have you
seem those small ARM7 parts from philips ? 32 bits at under $11 and quite
easy to interface and make work. Might be a option.. But... I am not the one
designing this beast.... It is up to the design guys to decide :-) I just
want something that can be built with easy to find parts...

> I also firmly believe a device such as this must be multifunction. A pure
> DSO is unlikely to excite folk. A 16+ channel logic analyzer is a nice
> adjunct. And stuff like function generators become pretty easy once the
> former are done.

   Agreed... A small logic analyser is quite usefull if we have the right
trigger options. Just compare trigger is a pain to work with... It would be
nice to have at least 2 level triggering capabilities.

> If can model this around Altera's Cyclone, I have enough hardware here
> right now to start doing the FPGA stuff. The Cyclone is also cheap, has
> memory interface glue and IP for free, and has a sister PROM for
> programming on startup.

   Can we get those at Digikey ?? :-) If we can I think it is a great
option.. Let's define it and start working ;-)

Best regards,
Alexandre Guimaraes



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2004\09\17@210553 by David P Harris

picon face
Marc Nicholas wrote:

> Did you just say you'd do boards? :-)
>
> I've been preaching a bit about FPGAs the past couple of days (sorry).
> You need the speed and predictability (important) of a
> hardware-oriented solution here. I just can't see the use of a PIC
> here anywhere (and am glad this is under [EE]: because of that).
>
> I also firmly believe a device such as this must be multifunction. A
> pure DSO is unlikely to excite folk. A 16+ channel logic analyzer is a
> nice adjunct. And stuff like function generators become pretty easy
> once the former are done.
>
> If can model this around Altera's Cyclone, I have enough hardware here
> right now to start doing the FPGA stuff. The Cyclone is also cheap,
> has memory interface glue and IP for free, and has a sister PROM for
> programming on startup.
>
> -marc
>
Sounds good. I would add my vote for multiuse.  Can we use somethink
easire to program than PROM?  As we probably all have PIC programmers,
can we use something compatible, like a PIC?
David


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2004\09\17@232031 by Bob Ammerman

picon face
> Sounds good. I would add my vote for multiuse.  Can we use somethink
> easire to program than PROM?  As we probably all have PIC programmers,
> can we use something compatible, like a PIC?
> David

If the stupid 18F USB PIC would ever show up it could handle the host
interface and downloding the 'code' into the FPGA. Of course, we could also
use the FTDI FIFO chip with a random PIC, but that isn't nearly as pretty.

I don't think it makes sense to try to jam the USB stuff directly into the
FPGA.

BTW: if this ever really does go somewhere, I can do code for a PIC and also
the PC.

I think memory depth is one of the strengths of the design and we should be
sure to maintain a deep memory.

Bob Ammerman
RAm Systems

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2004\09\17@235515 by Alexandre Guimaraes

face picon face
Hi, Bob

> BTW: if this ever really does go somewhere, I can do code for a PIC and
also
> the PC.

   I do not see why it will not work out !! We already have someone to do
the programable logic stuff, someone to make the boards and someone to write
the software ! Let's just do it.... Let's see how many more people want to
join and make this thing work and we can take it off list and start defining
the project and make it work.

Best regards,
Alexandre Guimaraes


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2004\09\18@003306 by Josh Koffman

face picon face
I can't compete with others in terms of programming prowess, or design
knowledge. I am willing to help with Canadian distribution though. To
be honest, I just want one for me, and anything I can do to encourage
the project along, I'm willing to do.

Plus, I won't be able to do much for the next couple of weeks as my
computer time is spotty at best as I deal with some issues.

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
       -Douglas Adams

On Sat, 18 Sep 2004 00:55:36 -0300, Alexandre Guimaraes
<listasEraseMEspam.....logikos.com.br> wrote:
>     I do not see why it will not work out !! We already have someone to do
> the programable logic stuff, someone to make the boards and someone to write
> the software ! Let's just do it.... Let's see how many more people want to
> join and make this thing work and we can take it off list and start defining
> the project and make it work.
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2004\09\18@004004 by David P Harris

picon face
I'm in.
David
Canada

Alexandre Guimaraes wrote:

{Quote hidden}

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2004\09\18@031130 by Mike Singer

picon face
===========================================
If the stupid 18F USB PIC would ever show up it could handle the host
interface and downloding the 'code' into the FPGA. Of course, we could
also use the FTDI FIFO chip with a random PIC, but that isn't nearly as
pretty.
I don't think it makes sense to try to jam the USB stuff directly into
the FPGA.
===========================================

Googling with "PC-based DSO" gives a bunch of hits.

How about first one, hobbyist:

PC-based DSO

a26.lambo.student.liu.se/ ?section=hard&project=scope


...I've written a bit of VHDL using Xilinx Webpack 5.1 and verified that
a Spartan2 FPGA can do what I want fast enough without too much trickery
(deep pipelines etc). At least that's what the software claims... Most
of the logic will run at 100MHz, but the memory interface will run at
133MHz in order to provide enough bandwidth to store the 40 bits of
information in a 32 bit SRAM. The 133MHz clock is generated using the
CLKDLLs (delay locked loop) in the Spartan2 chip. The 100MHz clock is
first divided by 1.5 and then doubled.

I estimate that I can fit all the basic functions (triggering,
downsampling, storage) in a XC2S50 (50000 gate) part, but to provide
room for future upgrades and features I will use a XC2S100 or 150 chip.
A PQFP208 package will be used in either case.

========================================

Mike.

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2004\09\18@041637 by Alexandre Guimaraes

face picon face
Hi, Mike

> Googling with "PC-based DSO" gives a bunch of hits.
>
> How about first one, hobbyist:
>
> PC-based DSO
>
> a26.lambo.student.liu.se/ ?section=hard&project=scope

   That is a perfect example about the reason to design something new...
Most projects I have seen try to deal with tenths of mhz sampling rates. We
do not need that for microcontroller projects and if we really need we
probably have the money to buy something on the market. Something below 1mhz
is much easier to design, should be quite cheap and portable. I have looked
for quite a while and I either find "audio only" or truly sophisticate high
speed designs. I never found something in between.

   My basic requirements would be:

- between 200khz and 1mhz max sampling rate.
- Small
- Cheap
- Built on double sided boards
- Easy to find components
- 2 channels scope with 8 or 12 bits of resolution
- 16 channels logic analyser
- 2 level depth trigger logic
- using a PC ou a Palm to show the results
- At least 32K memory buffers.

Best regards,
Alexandre Guimaraes





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2004\09\18@051835 by Roland

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Hi

I was wondering what the front end would be for this?

As far as I know, the bit-scope uses a 40MHz sampling chip.
I looked it up, compared, and the other day I bought a few AD9283 chips,
100Mbps sampling rate, to do a project just like this. I really want a
portable scope!  (laptop based (or old laptop screen))

The AD chips look easy to use. I would've wanted to use some PC simm/dimm
for the memory.

Either way, I can proto a board if we're using the AD9283.

Regards
Roland Jollivet

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2004\09\18@055558 by 8859-1?Q?M=E1rcio_Barbiani?=

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I saw a project that uses a sampling circuit that captures data and send to
a palm top with custom software, the author said it works fine.


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2004\09\18@074118 by Bob J

picon face
Wow! I didn't think I'd get this much interest from my initial post.
I'm still considering buying a bitscope, but this thing definitely has
my interest.  I like the ideas of a deep memory along with 100MS/s a/d
for glitch capture.

Yes Altera calls the FLEX 8K a "mature device", so some redesign is
necessary.  I imagine it wouldn't be that difficult to implement in a
new Altera device.  Just for kicks I downloaded the software and
compiled it in VC++ .NET and it compiled just fine, and it ran on XP
using the allowio parallel port driver.  There are a just a few
hardware issues, like input protection, that can be easily fixed. But
definitely usb would be the way to go, and I imagine the scope could
easily be powered by the usb bus.

I think with all the talent here we could easily accomplish this.
First of all we'd have to decide what the first steps would be with
the hardware and software, divvy out the tasks and go from there.
I've already contacted the designer and I think the next step may be
to discuss the progression of his design with him, and see if its ok
with him to open source it.

Regards,
Bob
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2004\09\18@082031 by Mike Singer

picon face
Alexandre Guimaraes wrote:
>
>    My basic requirements would be:
>
> - between 200khz and 1mhz max sampling rate.
> - Small
> - Cheap
> - Built on double sided boards
> - Easy to find components
> - 2 channels scope with 8 or 12 bits of resolution
> - 16 channels logic analyser
> - 2 level depth trigger logic
> - using a PC ou a Palm to show the results
> - At least 32K memory buffers.


Alexandre,

I'd consider some Kickstart Kit/Eval Board/Dev Tools etc.
for Philips LPC2XXX.
This family of 60 MHz ARM7-core Flash microcontrollers
seems to get close to your requirements and is pretty cheap.

Side effect would be an experience in a field PICs won't
reach in a decade.
CPLDs, FPGAs, DSOs are good, but, I think, 32 bit Philip's
microcontrollers are much easier to start with for a good
PICster :-)


Best Regards.

Mike.





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2004\09\18@092116 by Howard Winter

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Alexandre,

On Fri, 17 Sep 2004 21:44:12 -0300, Alexandre Guimaraes wrote:

>    I can draw the boards, spend some money to make the prototype and I can
> make more boards to anyone participating at the project just for the cost of
> the boards as they come from the board house.

I may have misunderstood, but I thought Tom's project web site:  http://www.chocbar.demon.co.uk/  already had
the boards designed and includes the files needed to make them?  Or are we considering a redesign?

Cheers,


Howard Winter
St.Albans, England


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2004\09\18@095055 by David P Harris

picon face
Howard Winter wrote:

{Quote hidden}

We are looking at a redesign.  Tom had already made some mods to his
project, but I think he never updated the site with them.  The feeling
is that we can do better now with newer hardware, and that a USB based
design would be better than using a the parallel port.
David



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2004\09\18@102021 by Marc Nicholas

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On Fri, 17 Sep 2004, David P Harris wrote:

>> If can model this around Altera's Cyclone, I have enough hardware here
>> right now to start doing the FPGA stuff. The Cyclone is also cheap, has
>> memory interface glue and IP for free, and has a sister PROM for
>> programming on startup.
>> -marc
>>
> Sounds good. I would add my vote for multiuse.  Can we use somethink easire
> to program than PROM?  As we probably all have PIC programmers, can we use
> something compatible, like a PIC?

Not sure about other FPGAs, but with the Cyclones the PROM [sic] (they're
actually serial EEPROMs; not sure why Altera refer to them always as
PROMs) is programmed by the FPGA (!) which can be fed the data in a number
of ways, including via a serial port. Pretty straight-forward.

-marc

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2004\09\18@105830 by Alexandre Guimaraes

face picon face
Hi, Mike

   I already have some LPC2104 samples here with me :-) With a good analog
front end, a 2 channel AD converter and a USB interface chip we could have a
very nice instrument for about 60 bucks in boards and parts... If we go to
the tenths of mhz I think that it is better to use one of the designs that
already exist on the Net....

   Ir we decide for speeds up to 1msps, we can use a LPC or a scenix part,
analog front end with 2 or 3 different input "scales", the AD converter
could be something like a AD7924 (12 bits,1msps $8.81), AD7928 (12 bits,
1msps $9.31) or many others from AD or Maxim and we could use a FTDI part to
communicate with the PC. At those sample rates we could probably stay with
no onboard memory. That leaves us with a design with less that 10 chips and
a bunch of passives that can be done in a simple double sided board, simple
to design and cheap to execute....

best regards,
Alexandre Guimaraes


{Original Message removed}

2004\09\18@121259 by Sascha

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face
Very nice project!

If you need 2 strong arms ;)... I am your guy!
I don't think the onboard storage cannot be let out even if the USB has the
speed needed because of the operating system so called multitasking. An
onboard buffer is needed at least to prevent that.

Best regards,
Sascha

{Original Message removed}

2004\09\18@122315 by Mike Singer

picon face
Alexandre,

Thank you for summarizing the sub-thread.

Mike.


<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  I already have some LPC2104 samples here with me :-) With a good
analog front end, a 2 channel AD converter and a USB interface chip we
could have a very nice instrument for about 60 bucks in boards and
parts... If we go to the tenths of mhz I think that it is better to use
one of the designs that already exist on the Net....

   Ir we decide for speeds up to 1msps, we can use a LPC or a scenix
part, analog front end with 2 or 3 different input "scales", the AD
converter could be something like a AD7924 (12 bits,1msps $8.81), AD7928
(12 bits, 1msps $9.31) or many others from AD or Maxim and we could use
a FTDI part to communicate with the PC. At those sample rates we could
probably stay with no onboard memory. That leaves us with a design with
less that 10 chips and a bunch of passives that can be done in a simple
double sided board, simple to design and cheap to execute....
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

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2004\09\18@130205 by Marc Nicholas

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Shall we maybe set up a Yahoo Group or similar? I can host a web
page/software download on the Geekythings server, too.

-marc

On Fri, 17 Sep 2004, David P Harris wrote:

{Quote hidden}

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2004\09\18@135808 by Bob Axtell

face picon face
This project interests me, too. I have all the devcelopment tools, i.e.
OrCad 9X Layout/Capture,
PCAD2K Layout, access to cheap sources, etc.

Probably should be redesigned for newer components, of course. Might be
nice if the interface
was buffered so that USB 1.0 could be used; would allow older PCs.

--Bob

Bob J wrote:

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2004\09\18@145215 by Gus S.Calabrese

face
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I would like to participate.
--- I would like multi-function.  DSO, Logic analyzer, function
generator, signature analysis
--- USB 2.0 interface
--- 100Mbit/sec sampling rate

Just for whimsy I would like to add FORTH control words ( low priority )

Please include me.




Gus S Calabrese
303.964.9670 w/vm   303.908.7716 cell no vm
http://www.omegadogs.com
4337 Raleigh St
Denver, CO 80212

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2004\09\18@145325 by Alexandre Guimaraes

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Hi, Marc

> Shall we maybe set up a Yahoo Group or similar? I can host a web
> page/software download on the Geekythings server, too.
>
> -marc

   I just created... The homepage is
http://groups.yahoo.com/group/MultiAnalyser/ . There we have a files and
photos section and it is free....

   If anyone can thing of a better name....

   I did not leave the registration open or we will get those crazy spam
things... But everyone is very welcome..

   Let's start to make the Multi Analyser happen :-)

Best regards,
Alexandre Guimaraes



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2004\09\18@150416 by Bob J

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>    Ir we decide for speeds up to 1msps, we can use a LPC or a scenix part,

Why only 1MS/s?  I'm looking for one 100MS/s or better, for glitch
capture, and so the thing isn't obsolete in three years.  That's the
point of having a large memory.

Seriously guys I don't think it will take long to improve this design.
Here are the things I would like to see:

1.  Better front end to the adc for impedance matching.  (just copy
what's out there for the bitscope.)
2.  Use a more current fpga.
3.  USB.
4.  Keep the memory as it is.
5.  Add voltage/time cursors to the software.
6.  Better noise rejection on the board.

I vote for the yahoo group (as much as I hate them), since this isn't
relevant to pic discussion.

Regards,
Bob
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2004\09\18@153343 by Marc Nicholas

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That works for me :-)

On Sat, 18 Sep 2004, Alexandre Guimaraes wrote:

{Quote hidden}

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2004\09\18@153805 by Marc Nicholas

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Memory bandwidth is the limiting factor. ZBT/SRAM (which is probably the
best design choice for a number of reasons; I'll elaborate my reasoning
behind that if anyone is interested) tops out at 200Mhz.

It becomes somewhat arbitary what speed the device runs at below that
ceiling :-) You already have to have the skills to deal with the SRAM
timing.

-marc


On Sat, 18 Sep 2004, Bob J wrote:

{Quote hidden}

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2004\09\18@222815 by Alexandre Guimaraes

face picon face
Hi, Bob

> Why only 1MS/s?  I'm looking for one 100MS/s or better, for glitch
> capture, and so the thing isn't obsolete in three years.  That's the
> point of having a large memory.

   I have nothing against a 100msps scope but designing one is a real
design challenge.. Right from the beginning at the analog front end.... The
FPGA part of the problem is just a small one. Do we have available people to
make the analog front end and AD conversion at those speeds ?? Do you have
experience with analog design at those speeds ? I do not.. And having 2
40mhz scopes available I can say that I very rarely use anything over
200ksps and I believe that most embeeded designers also do not.. How much
would you expect that a 100msps DSO with deep memory would cost ?

> Seriously guys I don't think it will take long to improve this design.
>  Here are the things I would like to see:
>
> 1.  Better front end to the adc for impedance matching.  (just copy
> what's out there for the bitscope.)

   Great idea.. Is the project open source ? Can we use it at our own
designs without breaking copyrights ?

> 2.  Use a more current fpga.

   Agreed.. Altera has some quite nice parts.

> 3.  USB.

   That is the best option... We just loose the possibility of using
Palmtops to make a real portable device. Maybe we can make something with a
USB port and a serial interface also.

> 4.  Keep the memory as it is.

   32K ??

> 5.  Add voltage/time cursors to the software.

   They are essential to make the scope usable. That is the main attactive
for me with my gagescope.  The software is great to use.

> 6.  Better noise rejection on the board.

   That goes for the analog designer that will make the front end... We can
keep the digital noise far from the input circuitry.

> I vote for the yahoo group (as much as I hate them), since this isn't
> relevant to pic discussion.

   The group is already there and the homepage is
http://groups.yahoo.com/group/MultiAnalyser/

   We already have 11 people joined to the group and it is just some hours
old !! It seems that there are some interested people.

Best regards,
Alexandre Guimaraes




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2004\09\19@090150 by Bob Ammerman

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> Seriously guys I don't think it will take long to improve this design.
>  Here are the things I would like to see:
>
> 1.  Better front end to the adc for impedance matching.  (just copy
> what's out there for the bitscope.)
> 2.  Use a more current fpga.
> 3.  USB.
> 4.  Keep the memory as it is.
> 5.  Add voltage/time cursors to the software.
> 6.  Better noise rejection on the board.
>
> I vote for the yahoo group (as much as I hate them), since this isn't
> relevant to pic discussion.

7. Front end improvements: AC/DC coupling. Input amplifier and attenuator
for 1-2-5 steps.
8. More advanced triggering for the logic analyzer: at least 2 stages with
don't cares for each stage.

Bob Ammerman
RAm Systems

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2004\09\19@093036 by David P Harris

picon face
Bob Ammerman wrote:

>8. More advanced triggering for the logic analyzer: at least 2 stages with
>don't cares for each stage.
>  
>
Can someone explain what this is?  Never having used a logic analyzer, I
do not understand what "2 stages" means.
David


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2004\09\19@124101 by Bob Axtell

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Bob means that you can set up the capture to begin based on a set of
conditions
(such as channel 1=1, channel 2=0, and channel 3=1, but channel 4, 5, 6,
7 are
X (don't care).

A logic analyzser simply captures the data as it occurs. The key to good
utilization is
triggering techniques.

--Bob

David P Harris wrote:

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2004\09\19@131811 by Bob Ammerman

picon face
Instead of triggering on just a single pattern, you have to see one pattern
following another pattern.

Bob Ammerman

{Original Message removed}

2004\09\19@132846 by Alexandre Guimaraes

face picon face
Hi Bob,

> > I vote for the yahoo group (as much as I hate them), since this isn't
> > relevant to pic discussion.

   It is already there and we already have 27 member signed in for it ! The
homepage is http://groups.yahoo.com/group/MultiAnalyser/

> 7. Front end improvements: AC/DC coupling. Input amplifier and attenuator
> for 1-2-5 steps.

   That helps a lot, it is one of the annoying things of the Bitscope. The
weird attenuator values.

> 8. More advanced triggering for the logic analyzer: at least 2 stages with
> don't cares for each stage.

   That is essencial. I have a logic analyser that just triggers in one
stage and it is almost impossible to use for many tasks. Another important
thing on the logic analyser side is the clock generator. It has to be
flexible to accomodate the different uses and external clock is also a nice
thing to have if we go the FPGA way...

Best regards,
Alexandre Guimaraes


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2004\09\19@141543 by Herbert Graf

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On Sat, 2004-09-18 at 15:33, Marc Nicholas wrote:
> Memory bandwidth is the limiting factor. ZBT/SRAM (which is probably the
> best design choice for a number of reasons; I'll elaborate my reasoning
> behind that if anyone is interested) tops out at 200Mhz.

Actually I don't consider memory bandwidth the limit at all. There is
nothing to say that your memory has to be only as wide as the sample
size, you could use 128bit wide memory and capture 2 8 bit samples at a
time, meaning one memory access could store 8 samples, turning your
200MHz memory speed into 800MSps.

Or, another similar way is to use memory banks, 4 banks of memory each
selected in order.

TTYL

-----------------------------
Herbert's PIC Stuff:
http://repatch.dyndns.org:8383/pic_stuff/

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2004\09\19@173337 by Alexandre Guimaraes

face picon face
Hi,

> Bob Ammerman wrote:
>
> >8. More advanced triggering for the logic analyzer: at least 2 stages
with
> >don't cares for each stage.
> >
> >
> Can someone explain what this is?  Never having used a logic analyzer, I
> do not understand what "2 stages" means.

   Sometimes you want to trigger on more "complex events" than what can be
described by just one moment. For example: if you want to trigger at the
beggining of the first bit on a serial data stream and not at the start bit
beggining. You would set a 2 stage trigger to trigger when the signal goes
from 1 to 0 and then from 0 to 1... That will happen exactly at the end of
the start bit and the beggining of the first bit.

   I am not sure if that is clear enough but the basic idea is to be able
to trigger when you have a set of events in consecutive moments of the
signal you are trying to looking at.

Best regards,
Alexandre Guimaraes


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2004\09\20@052021 by hael Rigby-Jones

picon face
>Alexandre,
>
>On Fri, 17 Sep 2004 21:44:12 -0300, Alexandre Guimaraes wrote:
>
>>    I can draw the boards, spend some money to make the
>prototype and I
>> can make more boards to anyone participating at the project just for
>> the cost of the boards as they come from the board house.
>

>{Original Message removed}

2004\09\25@111138 by Ken Pergola

flavicon
face

This might give some ideas to the collaboration project in this thread:

I'm sure others have already seen this by now, but for those who have not,
in the latest issue of Circuit Cellar (October 2004), Larry Cicchinelli of
Z-World has a "Single-Board Logic Analyzer" project article. He claims it
can be built for around $60 USD. It might not fit the needs of this thread
in all respects, but it might be worth checking out.

Best regards,

Ken Pergola


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2004\09\25@111442 by Ken Pergola
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I wrote:

> ...in the latest issue of Circuit Cellar (October 2004),
> Larry Cicchinelli of Z-World has a "Single-Board Logic Analyzer"
> project article.

Sorry, I forgot to post the link to his web site:

http://www.qsl.net/k3pto/


Best regards,

Ken Pergola

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2004\09\25@121617 by Alexandre Guimaraes

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Hi,

   The project in the group made to discuss the scope project is going on
pretty fast.

   We already have 53 members there and 156 messages in these few days that
it is going on...

   We still need some more talents to the group. If anyone else is
interested please take a look there and if possible volunteer to help :-)

   We need some good analog guys and programable logic people..


   Group homepage: http://groups.yahoo.com/group/MultiAnalyser/

best regards,
Alexandre Guimaraes


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2004\09\25@162208 by Richard Benfield

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you don't need more talent you've got bob ;o)
----- Original Message -----
From: "Alexandre Guimaraes" <RemoveMElistasspam_OUTspamKILLspamlogikos.com.br>
To: "Microcontroller discussion list - Public." <RemoveMEpiclistTakeThisOuTspamspammit.edu>
Sent: Saturday, September 25, 2004 5:16 PM
Subject: Re: [EE] scope project anyone?


> Hi,
>
>     The project in the group made to discuss the scope project is going on
> pretty fast.
>
>     We already have 53 members there and 156 messages in these few days
that
{Quote hidden}

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2004\09\27@153413 by Alexandre Guimaraes

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Hi

> you don't need more talent you've got bob ;o)

   :-) .....

   You are almost right.... But the project has gotten to be more complex
than initially planned, we are going to 100 Msps, modular approach with USB,
Ethernet and maybe firewire options... And we really could use a very good
analog expert and our FPGA guy has not appeared in the last few days... We
may need one more..

   Talented people is never enough.... The piclist is a good example ;-)

Best regards,
Alexandre Guimaraes



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2004\09\28@012207 by Richard Benfield

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That's why I've almost given up on it. the front end is starting to sound
like a frontend of a "software radio" and not like a scope.
there's no need for more than usb1, or more than 100ksamples per channel.
I have a feeling that it will never get finished. Or that the majority wont
invest in the hardware until its proven to work by quite a number of people
due to the high cost.
{Original Message removed}

2004\09\28@032623 by Jason S

flavicon
face
I agree with you.  It sounds like the project is getting an impossible list
of features before design even starts.  The way it's going, it will never
get off the ground because people will get overwhelmed and lose interest as
month go by with no real progress.

I'd like to see a fairly basic model working before even attempting adding
frills.  Things like ethernet will add complexity while not adding anything
useful.  Insanely high sampling rates will make every aspect of the design
needlessly difficult and expensive.

The project sounds very interesting to me and I did join the yahoo group.
It's very disappointing to see it running into these problems already.

Jason


From: "Richard Benfield" <EraseMEspacecatspamspamspamBeGone450se.co.uk>
Sent: Monday, September 27, 2004 10:22 PM


> That's why I've almost given up on it. the front end is starting to sound
> like a frontend of a "software radio" and not like a scope.
> there's no need for more than usb1, or more than 100ksamples per channel.
> I have a feeling that it will never get finished. Or that the majority
wont
> invest in the hardware until its proven to work by quite a number of
people
> due to the high cost.

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2004\09\28@050122 by Russell McMahon

face
flavicon
face
>... It sounds like the project is getting an impossible list
> of features before design even starts.  The way it's going, it will never
> get off the ground because people will get overwhelmed and lose interest
> as
> month go by with no real progress.

I see some merit in making a "wish list", assigning each a resource cost and
then seeing how people rate them. I don't see a 100 MSPS sampling rate as
overly difficult (I may be wrong :-) ). IF the A2D, memories and control
logic can handle this rate then it's not tooo much harder than say 20 MSPS
or even 1 MSPS and may cost little more.

People talking about 100 KSPS and 100 MSPS are talking about completely
different devices (shopping basket vs rally car). If this is happening it's
clear that people haven't sat down and worked out what the basic
capabilities and needs for this device are.

Things like ethernet interfaces could be handled in an add on modular manner
(both in hardware and software). It could be that people value this when the
resource cost is known, and maybe not. It could be that such a module could
be added by someone who is keen and expert in this area with relatively
little effort. (Ethernet takes about 1 IC and a little glue plus requisite
system I/O lines.)

If all people want is 100 KSPS then all you need is a bare PIC :-)
(Or maybe a bare PIC plus a deepish widish memory that you can stuff sample
data into rapidly enough). You can buy "scopes" that do this at very modest
prices.

Why not make a comprehensive list of POSSIBLE features, grouped functionally
and then have people place estimates on their implementation cost and effect
on final cost. Brief comments on relevant factors could be added.

eg Sample Rate:

<=  X KBPS Can be handled by PIC onboard A2D

X   - Y MBPS can be handled by external A2D with PIC transferring data fro
A2D to external memory

> Y MBPS data acquisition and storage managed by hardware.

Up to S1 MBPS uses available low cost A2D and xxx memory.
Up to S2 MBPS A2D speed is limit.
Up to S3 MBPS reasonably priced memory speed is limit ...

etc
whatever.



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2004\09\28@144914 by Mike Singer

picon face
> &#8230;The project sounds very interesting to me and
> I did join the yahoo group. It's very disappointing
> to see it running into these problems already&#8230;

What's the logic behind the setting up the yahoo group? Is [EE]
channel overloaded? Perhaps I'm missing something very specific for I
didn't read the thread.

Two years ago famous PBK project had eaten up almost thousand posts,
if I'm not mistaken, and nobody objected. Does anybody remember that
stupid discussion about 16F vs 18F and Olin was the first who openly
admitted that a newbie should start with PIC18FXXX rather than with
PIC16FXXX.

Mike.
-------
"One generation passeth away, and another generation cometh, but the
Earth abideth forever&#8230; The sun also ariseth, and the sun goeth down
and hasteth to the place where he arose&#8230; The wind goeth toward the
south, and turneth about unto the north; it whirleth about
continually, and the wind returneth again according to his circuits.
&#8230;All the rivers run into the sea; yet the sea is not full; unto the
place from whence the rivers come, thither they return again."
                                                          -- Ecclesiastes

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2004\09\28@152359 by Alexandre Guimaraes

face picon face
Hi, Mike


> …The project sounds very interesting to me and
> I did join the yahoo group. It's very disappointing
> to see it running into these problems already…

>What's the logic behind the setting up the yahoo group? Is [EE]
>channel overloaded? Perhaps I'm missing something very specific for I
>didn't read the thread.

   The idea is not to dumb on the list even more messages than it gets
everyday for a very specific project. We are trying to keep people posted
about the progress and anyone that is dearly interested can jump into the
Yahoo group with us.. We already have about a couple hundred messages there
in a few days and the majority of them do not have much usefull technical
information out of the project.

   When we make big steps in the design or when we need more help I intend
to "publish" it he on the list.

best regards,
Alexandre Guimaraes

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2004\09\28@161255 by Jason S

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From: "Russell McMahon" <RemoveMEapptechKILLspamspamparadise.net.nz>
Sent: Tuesday, September 28, 2004 1:48 AM


> I see some merit in making a "wish list", assigning each a resource cost
and
> then seeing how people rate them. I don't see a 100 MSPS sampling rate as
> overly difficult (I may be wrong :-) ). IF the A2D, memories and control
> logic can handle this rate then it's not tooo much harder than say 20 MSPS
> or even 1 MSPS and may cost little more.

There's nothing wrong with a wish list, but it seems like these are all
basic design criteria.  It's true that "overly difficult" is a relative
term, but 100 MSPS involves having to deal with a very large amount of
bandwidth.  Would firewire even be fast enough or we have to start dealing
with data compression?  The probes also get a lot more expensive and the
circuitry handling the signal inside has to be much more precise to avoid
introducing noise.

> People talking about 100 KSPS and 100 MSPS are talking about completely
> different devices (shopping basket vs rally car).

Good analogy.  I might make a shopping basket in my garage, but I don't have
the skill or tools to make a rally car, even from someone else's plans or
kit.

> Things like ethernet interfaces could be handled in an add on modular
manner
> (both in hardware and software).

Agreed, as long as the project concentrates on getting the basic unit
working before designing the add-ons.  The add-ons are useless if the basic
unit is never finished.

It seems that things like ethernet interfaces are becoming part of the basic
design though.

> If all people want is 100 KSPS then all you need is a bare PIC :-)
> (Or maybe a bare PIC plus a deepish widish memory that you can stuff
sample
> data into rapidly enough). You can buy "scopes" that do this at very
modest
> prices.

That's actually what I thought the project was originally.

Jason

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2004\09\28@164143 by Dave VanHorn

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>
>> People talking about 100 KSPS and 100 MSPS are talking about completely
>> different devices (shopping basket vs rally car).
>
>Good analogy.  I might make a shopping basket in my garage, but I don't have
>the skill or tools to make a rally car, even from someone else's plans or
>kit.

Take a page from the Tek 7000 line.
Make different front ends, that plug in.

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2004\09\28@230608 by Mike Singer

picon face
Hi, Alexandre.

>   The idea is not to dumb on the list even more messages
> than it gets everyday for a very specific project.

I can't say for James, but I'd suggest that some dozens of extra
EE-related posts a day couldn't kill PICList.

> We are trying to keep people posted about the progress and
> anyone that is dearly interested can jump into the Yahoo group
> with us..

You are building and promoting yet another community using PICList
channel without explicit permission of the List owner. Can't say for
James, but I'm not sure it's okay from the ethic point of view.

> We already have about a couple hundred messages there
> in a few days and the majority of them do not have much
> useful technical information out of the project.

That's just your opinion, others may have different.

Best Regards.

Mike.
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2004\09\29@021311 by David P Harris

picon face
Umm, I think you have to give the project a little time --- you can't
expect a group project to come together very quickly.
I think progress is being made.
David


Richard Benfield wrote:

>That's why I've almost given up on it. the front end is starting to sound
>like a frontend of a "software radio" and not like a scope.
>there's no need for more than usb1, or more than 100ksamples per channel.
>I have a feeling that it will never get finished. Or that the majority wont
>invest in the hardware until its proven to work by quite a number of people
>due to the high cost.
>{Original Message removed}

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