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'[EE] flash endurance'
2007\10\30@155935 by alan smith

picon face
Software dude said.....the endurance of a flash is only related to the erase cycles, not the write cycles....ie....you get longer endurance if you only write thru a sector and then erase the entire sector..vs...erasing each location if you want/need to overwrite it.
 
 True or false?

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2007\10\30@163434 by Walter Banks

picon face
One data point. About 5 years ago we cycled flash until it failed.
Most every processor flash started failing at about 10 times the
rated cycles. All the tests were done at room temperature.

At the time manufacturer independent. What it did was
establish to us that we could depend on published spec's.

The automotive folks use various error correction schemes to
maintain odometer readings with power off. They include
multiple copies and checksum/crc validation.

Regards

--
Walter Banks
Byte Craft Limited
Tel. (519) 888-6911
Fax (519) 746 6751
http://www.bytecraft.com
spam_OUTwalterTakeThisOuTspambytecraft.com


alan smith wrote:

> Software dude said.....the endurance of a flash is only related to the erase cycles, not the write cycles....ie....you get longer endurance if you only write thru a sector and then erase the entire sector..vs...erasing each location if you want/need to overwrite it.
>
>   True or false?
>
>  __________________________________________________
> Do You Yahoo!?
> Tired of spam?  Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
> -

2007\10\30@175252 by Jinx

face picon face
> Software dude said.....the endurance of a flash is only related to
> the erase cycles, not the write cycles....ie....you get longer endurance
> if you only write thru a sector and then erase the entire sector..vs...
> erasing each location if you want/need to overwrite it.
>
> True or false?

For some reason I haven't received the original post, but if you're
quoting correctly, then it's true - he did say that ;-)

The topic has been covered here now and then, you should be able
to find previous discussions in the archives

Flash erase and write are inextricably linked. Take any PIC that
can write to its own Flash. For example, to change one Flash byte

- read the Flash block into RAM, modify the byte
- erase the Flash block
- write RAM back into the Flash


>From http://en.wikipedia.org/wiki/Flash_memory

Although technically a type of EEPROM, the term "EEPROM"
is generally used to refer specifically to non-flash EEPROM which
is erasable in small blocks, typically bytes
.....
One limitation of flash memory is that although it can be read or
programmed a byte or a word at a time in a random access
fashion, it must be erased a "block" at a time. This generally sets
all bits in the block to 1. Starting with a freshly erased block, any
location within that block can be programmed. However, once
a bit has been set to 0, only by erasing the entire block can it be
changed back to 1. In other words, flash memory (specifically
NOR flash) offers random-access read and programming
operations, but cannot offer arbitrary random-access rewrite or
erase operations

>From Microchip AN537 -

http://ww1.microchip.com/downloads/en/AppNotes/00537.pdf

Figure 1 illustrates a CMOS floating gate EEPROM cell, including
voltage conditions for READ, ERASE, and WRITE operations. To
erase or write, the row select transistor must have the relatively high
potential of 20V. This voltage is internally generated on chip by a
charge pump, with the only external voltage required being VDD.

The only difference between an ERASE and a WRITE is the direction
of the applied field potential relative to the polysilicon floating gate.

When 20V is applied to the polysilicon memory cell gate and 0V is
applied to the bit line drain (column), electrons tunnel from the
substrate through the 90-angstrom Tunnel Dielectric (TD) oxide to
the polysilicon floating gate until the polysilicon floating gate is
saturated with charge. The cell is now at an ERASE state of "1"

When 0V is applied to the polysilicon memory cell gate and 20V is
applied to the bit line drain (column), electrons tunnel from the
polysilicon floating gate through the TD oxide to the substrate. The
cell then is at a WRITE state of "0". This sequence of the transfer
of charge onto the floating gate (ERASE) and the electrical removal
of that charge from the floating gate (WRITE) is one ERASE/ WRITE
cycle, or "E/W cycle."

The field (applied voltage to an oxide thickness) across the tunneling
path created by the 20V potential is extremely high in order to
transfer the electrons. Over the cell's "application time," as measured
by E/W cycles, the EEPROM cell begins to wear out due to the field
stress.

The EEPROM cell wears out as the number of cycles increase
resulting in the voltage margin between the ERASE and WRITE
states decreasing until finally there is not enough margin for the
EEPROM sense amp to detect a difference in the two states during
a READ. Failure is defined as when the sense amp can no longer
reliably differentiate logic state changes


2007\10\30@181336 by peter green

flavicon
face

> Flash erase and write are inextricably linked. Take any PIC that
> can write to its own Flash.

Not true, flash cells erase to a state (in the case of pics logic 1) and
can be changed to another state (in the case of pics logic 0) by the
programming process. The important point being if you only want to
change ones to zeros and not zeros to ones you don't have to erase.


2007\10\30@184342 by Jinx

face picon face
> The important point being if you only want to change ones to
> zeros and not zeros to ones you don't have to erase

It would have to be erased to get in the all 1 state to start with. A
sequence such as 11111111, 01111111, 00111111 .... 00000000
would be far less common generally than a 1/0 mix, eg data or code

Like re-programmng - the addition of one instruction will probably
put a new pattern in most locations after that, requiring erasure. Even
those that aren't changed would still be erased first. AFAIK most
programmers would not selectively erase

Code re-programming endurance is probably not relevant though
(unless you take a reeeeaaallllly long time to get a program right),
but data endurance is

2007\10\30@190810 by stef mientki

picon face
Jinx wrote:
>> The important point being if you only want to change ones to
>> zeros and not zeros to ones you don't have to erase
>>    
>
> It would have to be erased to get in the all 1 state to start with. A
> sequence such as 11111111, 01111111, 00111111 .... 00000000
> would be far less common generally than a 1/0 mix, eg data or code
>
> Like re-programmng - the addition of one instruction will probably
> put a new pattern in most locations after that, requiring erasure. Even
> those that aren't changed would still be erased first. AFAIK most
> programmers would not selectively erase
>
> Code re-programming endurance is probably not relevant though
> (unless you take a reeeeaaallllly long time to get a program right),
> but data endurance is
>
>  
and if you're talking about PICs,
look at this:
http://oase.uci.kun.nl/~mientki/data_www/pic/libs_hw/eeprom_problems.html

cheers,
Stef

2007\10\30@192006 by Jinx

face picon face
> and if you're talking about PICs, look at this:
>
> http://oase.uci.kun.nl/~mientki/data_www/pic/libs_hw/eeprom_problems.html

It's worth searching Microchip app notes for 'endurance'. MC
also have downloadable predictive s/w

2007\10\31@110335 by alan smith

picon face
Very good post...very interesting.....much appreciated.  The issue that I am facing is they are writing setup parameters that may get changed by the user rather frequently so each time some is adjusted...it gets written out to storage so on power cycle it comes back to the last known state.  They have requirements from some customers that in order to get into them, it has to have at least a 20 year retention.
 
 So, I was introduced to FRAM memory yesterday by a vendor.  Anyone used that before?  Non-volitile, long retention and not the issues off flash.  And not very expensive....so I am told.  Still waiting on pricing.

Jinx <.....joecolquittKILLspamspam@spam@clear.net.nz> wrote:
 > Software dude said.....the endurance of a flash is only related to
> the erase cycles, not the write cycles....ie....you get longer endurance
> if you only write thru a sector and then erase the entire sector..vs...
> erasing each location if you want/need to overwrite it.
>
> True or false?

For some reason I haven't received the original post, but if you're
quoting correctly, then it's true - he did say that ;-)

The topic has been covered here now and then, you should be able
to find previous discussions in the archives

Flash erase and write are inextricably linked. Take any PIC that
can write to its own Flash. For example, to change one Flash byte

- read the Flash block into RAM, modify the byte
- erase the Flash block
- write RAM back into the Flash


>From http://en.wikipedia.org/wiki/Flash_memory

Although technically a type of EEPROM, the term "EEPROM"
is generally used to refer specifically to non-flash EEPROM which
is erasable in small blocks, typically bytes
.....
One limitation of flash memory is that although it can be read or
programmed a byte or a word at a time in a random access
fashion, it must be erased a "block" at a time. This generally sets
all bits in the block to 1. Starting with a freshly erased block, any
location within that block can be programmed. However, once
a bit has been set to 0, only by erasing the entire block can it be
changed back to 1. In other words, flash memory (specifically
NOR flash) offers random-access read and programming
operations, but cannot offer arbitrary random-access rewrite or
erase operations

>From Microchip AN537 -

http://ww1.microchip.com/downloads/en/AppNotes/00537.pdf

Figure 1 illustrates a CMOS floating gate EEPROM cell, including
voltage conditions for READ, ERASE, and WRITE operations. To
erase or write, the row select transistor must have the relatively high
potential of 20V. This voltage is internally generated on chip by a
charge pump, with the only external voltage required being VDD.

The only difference between an ERASE and a WRITE is the direction
of the applied field potential relative to the polysilicon floating gate.

When 20V is applied to the polysilicon memory cell gate and 0V is
applied to the bit line drain (column), electrons tunnel from the
substrate through the 90-angstrom Tunnel Dielectric (TD) oxide to
the polysilicon floating gate until the polysilicon floating gate is
saturated with charge. The cell is now at an ERASE state of "1"

When 0V is applied to the polysilicon memory cell gate and 20V is
applied to the bit line drain (column), electrons tunnel from the
polysilicon floating gate through the TD oxide to the substrate. The
cell then is at a WRITE state of "0". This sequence of the transfer
of charge onto the floating gate (ERASE) and the electrical removal
of that charge from the floating gate (WRITE) is one ERASE/ WRITE
cycle, or "E/W cycle."

The field (applied voltage to an oxide thickness) across the tunneling
path created by the 20V potential is extremely high in order to
transfer the electrons. Over the cell's "application time," as measured
by E/W cycles, the EEPROM cell begins to wear out due to the field
stress.

The EEPROM cell wears out as the number of cycles increase
resulting in the voltage margin between the ERASE and WRITE
states decreasing until finally there is not enough margin for the
EEPROM sense amp to detect a difference in the two states during
a READ. Failure is defined as when the sense amp can no longer
reliably differentiate logic state changes


2007\10\31@113345 by Alan B. Pearce

face picon face
> They have requirements from some customers that in order
>to get into them, it has to have at least a 20 year retention.

Grief, what sort of equipment is it?  

2007\10\31@123545 by alan smith

picon face
ummm....bout all I can say is its a DSP centric processing board....multiple high end DSP's.
 
 You know how some certain three letter gov't groups are....

"Alan B. Pearce" <A.B.PearcespamKILLspamrl.ac.uk> wrote:
 > They have requirements from some customers that in order
>to get into them, it has to have at least a 20 year retention.

Grief, what sort of equipment is it?

2007\10\31@132550 by Alan B. Pearce

face picon face
>You know how some certain three letter gov't groups are....

Umm, yeah, in our case it takes ten years to reach the planet before you can
do any work ...

2007\10\31@171952 by alan smith

picon face
There is also Freescale MRAM, similar to FRAM it seems.  But not in serial only parallel

"Alan B. Pearce" <.....A.B.PearceKILLspamspam.....rl.ac.uk> wrote:  >You know how some certain three letter gov't groups are....

Umm, yeah, in our case it takes ten years to reach the planet before you can
do any work ...

2007\10\31@204853 by Russell McMahon

face
flavicon
face
>>> They have requirements from some customers that in order
>> to get into them, it has to have at least a 20 year
>> retention.

>> Grief, what sort of equipment is it?


>  ummm....bout all I can say is its a DSP centric
> processing board....multiple high end DSP's.
>  You know how some certain three letter gov't groups
> are....


Ah` ! - It must be the NS@!!!#!!


                           Russenl


[[ Just possibly an original joke :-) ]]

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