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'[EE] Soldermask and vias?'
2012\03\25@125658 by Matt Bennett

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I'm sitting here working on a board, and I can't figure out something- it
seems like tradition that you don't put your soldermask over a via- that's
the default in Eagle* and how it has worked out in most layouts I've done.
Is there good reason for this with modern PCB fab equipment? I realize
that an un-masked via makes for an easy rework/test point.  I can also see
that I may not want to put mask over a hole (where there isn't board to
cover), but the silkscreen also seems to be left off where there isn't
mask, and I want to make sure I don't mess with my silkscreen (if I need
to get at the via, I'd rather scrape off the mask/silkscreen).

A friend got burned by poor plating a long time ago, and on his protos,
insists on filling the vias with solder- just in case the plating was
poor. Valid, but I haven't seen a bad via on my boards in years- if the
vias are that bad, there probably are other problems.

A google search came up with the possibility of trapping chemicals under
the mask in a drill hole, but that sounds like a more fundamental issue
with the manufacturing process.

Regards,

Matt

* You can adjust this property in Eagle Layout under 'DRC' -> 'Masks'

Matt Bennett
Just outside of Austin, TX
30.51,-97.91

The views I express are my own, not that of my employer, a large
multinational corporation that you are familiar with

2012\03\25@131550 by Josh Koffman

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On Sun, Mar 25, 2012 at 12:56 PM, Matt Bennett <spam_OUTmattpiclistTakeThisOuTspamhazmat.com> wrote:
> I'm sitting here working on a board, and I can't figure out something- it
> seems like tradition that you don't put your soldermask over a via- that's
> the default in Eagle* and how it has worked out in most layouts I've done..
> Is there good reason for this with modern PCB fab equipment? I realize
> that an un-masked via makes for an easy rework/test point.  I can also see
> that I may not want to put mask over a hole (where there isn't board to
> cover), but the silkscreen also seems to be left off where there isn't
> mask, and I want to make sure I don't mess with my silkscreen (if I need
> to get at the via, I'd rather scrape off the mask/silkscreen).

I can't offer more than anecdotal evidence on this, but it's something
I thought about a bit last year. I used to get PCBs done with no
soldermask as I was using a proto house and never made more than a
couple of each board. I finally switched to a production house and
suddenly there were new things to consider!

While I can't say if it's "better" to do it one way or another, I
think esthetically it's a bit more pleasing to my eye to have the via
tented. They seem to do it on all sorts of complex computer PCBs
(motherboards, etc), so that's a vote in its favour. In addition, the
guys at Sparkfun recommend in their PCB tutorial.

Josh
-- A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
        -Douglas Adams

2012\03\25@145510 by alan.b.pearce

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> I'm sitting here working on a board, and I can't figure out something-
> it seems like tradition that you don't put your soldermask over a via-
> that's the default in Eagle* and how it has worked out in most layouts
> I've done.

The problem that arises is that the solder resist will flow down the hole in the via, leaving possible thinning of the resist at the hole edge. If the via was not plated as it would be covered by resist then the thinning of the resist may leave exposed unplated copper.

> Is there good reason for this with modern PCB fab equipment? I realize
> that an un-masked via makes for an easy rework/test point.  I can also
> see that I may not want to put mask over a hole (where there isn't
> board to cover), but the silkscreen also seems to be left off where
> there isn't mask, and I want to make sure I don't mess with my
> silkscreen (if I need to get at the via, I'd rather scrape off the
> mask/silkscreen).

One of the tricks for insisting on solder resist over vias is filling vias with something before the resist screening process so the resist doesn't flow down the hole. This becomes another step in the process, adding cost, another inspection step, and may also require polishing to ensure the filling is not proud before the resist is screened on.

> A friend got burned by poor plating a long time ago, and on his protos,
> insists on filling the vias with solder- just in case the plating was
> poor. Valid, but I haven't seen a bad via on my boards in years- if the
> vias are that bad, there probably are other problems.

That would be either a very long time ago while the process was getting well sorted, or it was a manufacturer just setting up PTH process, and not yet familiar with the process control requirements. If one has a problem with via quality these days then the manufacturer should be shouted at very loudly.

> A google search came up with the possibility of trapping chemicals
> under the mask in a drill hole, but that sounds like a more fundamental
> issue with the manufacturing process.

If that is a problem, then it will be just as much a problem if the resist doesn't cover the via because it says the board hasn't been washed properly to some stage, leading  to the likelihood of the trapped chemicals eating away at the metal anyway.


-- Scanned by iCritical.

2012\03\25@151421 by Mike Harrison

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>> A friend got burned by poor plating a long time ago, and on his protos,
>> insists on filling the vias with solder- just in case the plating was
>> poor. Valid, but I haven't seen a bad via on my boards in years- if the
>> vias are that bad, there probably are other problems.
>
>That would be either a very long time ago while the process was getting well sorted, or it was a manufacturer just setting up PTH process, and not yet familiar with the process control requirements. If one has a problem with via quality these days then the manufacturer should be shouted at very loudly.

You may want to solder-fill vias to help in high current or high thermal load situations, on
flow-soldered PCBs,  although relying on it would probably mean you'd want to inspect to make sure
they got filled.

2012\03\25@164655 by alan.b.pearce
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> >> A friend got burned by poor plating a long time ago, and on his
> >> protos, insists on filling the vias with solder- just in case the
> >> plating was poor. Valid, but I haven't seen a bad via on my boards
> in
> >> years- if the vias are that bad, there probably are other problems.
> >
> >That would be either a very long time ago while the process was
> getting well sorted, or it was a manufacturer just setting up PTH
> process, and not yet familiar with the process control requirements. If
> one has a problem with via quality these days then the manufacturer
> should be shouted at very loudly.
>
> You may want to solder-fill vias to help in high current or high
> thermal load situations, on flow-soldered PCBs,  although relying on it
> would probably mean you'd want to inspect to make sure they got filled.

When doing space flight qualified PCBs there are two options, don't fill the via at all, or fully fill it. This follows some research that IBM did some years ago when researching thermal cycling problems with PTH PCBs.
AIUI there is no preference either way, and for all our boards we go with unfilled vias unless there is a specific thermal or current carrying capacity requirement, or inspection of the soldering work shows that a via has had solder start to fill a via.
-- Scanned by iCritical.

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