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'[EE] Soldering BGA'
2011\05\08@094935 by V G

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Hey all,

I'm thinking of making a Spartan 6 FPGA board of my own for a cheap
price. I'll need to get the board made professionally, probably 2
layer. If I get a BGA chip, how would I go about soldering that when
all the components and the board arrive?

Would I need to reflow it in my toaster? Or can I use my hot air
rework station and blow hot air at it?

Then there's the problem with alignment..

2011\05\08@095521 by Bob Ammerman

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> Hey all,
>
> I'm thinking of making a Spartan 6 FPGA board of my own for a cheap
> price. I'll need to get the board made professionally, probably 2
> layer. If I get a BGA chip, how would I go about soldering that when
> all the components and the board arrive?
>
> Would I need to reflow it in my toaster? Or can I use my hot air
> rework station and blow hot air at it?
>
> Then there's the problem with alignment...

Any decent size BGA is not going to work on a 2-layer board.

-- Bob Ammerman
RAm Systems

2011\05\08@101353 by V G

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On Sun, May 8, 2011 at 9:55 AM, Bob Ammerman <spam_OUTrvammermanTakeThisOuTspamroadrunner.com> wrote:
> Any decent size BGA is not going to work on a 2-layer board.

I'm thinking between 100 and 200 pins. So it needs to be 4 layer

2011\05\08@104704 by Oli Glaser

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On 08/05/2011 15:13, V G wrote:
> On Sun, May 8, 2011 at 9:55 AM, Bob Ammerman<.....rvammermanKILLspamspam@spam@roadrunner.com>  wrote:
>> Any decent size BGA is not going to work on a 2-layer board.
> I'm thinking between 100 and 200 pins. So it needs to be 4 layer?

At the very least - I made a 2-layer test board for a 64 pin FPGA that "worked", but for any serious use you need power and ground planes for decoupling and controlled impedance purposes, plus the extra routing space. Look into high speed digital techniques and you will see why all this is necessary. Xilinx should have some relevant documentation on their site, about the optimum setup for their chips, how many IOs can switch at once, thermal considerations, etc.

2011\05\08@110822 by Mike Harrison

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On Sun, 08 May 2011 15:46:28 +0100, you wrote:

>On 08/05/2011 15:13, V G wrote:
>> On Sun, May 8, 2011 at 9:55 AM, Bob Ammerman<rvammermanspamKILLspamroadrunner.com>  wrote:
>>> Any decent size BGA is not going to work on a 2-layer board.
>> I'm thinking between 100 and 200 pins. So it needs to be 4 layer?
>
>At the very least - I made a 2-layer test board for a 64 pin FPGA that
>"worked", but for any serious use you need power and ground planes for
>decoupling and controlled impedance purposes, plus the extra routing
>space. Look into high speed digital techniques and you will see why all
>this is necessary. Xilinx should have some relevant documentation on
>their site, about the optimum setup for their chips, how many IOs can
>switch at once, thermal considerations, etc.

QFP packaged FPGAs, however are entirely viable on 2 layers, as long as you only have one I/O
voltage, as this can be on a top-side plane under the chip.

2011\05\08@110959 by V G

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On Sun, May 8, 2011 at 10:46 AM, Oli Glaser <.....oli.glaserKILLspamspam.....talktalk.net> wrote:
> At the very least - I made a 2-layer test board for a 64 pin FPGA that
> "worked", but for any serious use you need power and ground planes for
> decoupling and controlled impedance purposes, plus the extra routing
> space. Look into high speed digital techniques and you will see why all
> this is necessary. Xilinx should have some relevant documentation on
> their site, about the optimum setup for their chips, how many IOs can
> switch at once, thermal considerations, etc.

Looks like I need a degree in EE.

I'll go sit in the EE lectures at my university in my spare time next
year. This looks like some serious stuff

2011\05\08@111631 by Nathan Nottingham

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On May 8, 2011, at 07:49 AM, V G wrote:

> Would I need to reflow it in my toaster? Or can I use my hot air
> rework station and blow hot air at it?
>
> Then there's the problem with alignment...
> —
I've done quite a bit of amateur BGA rework with large pin count chips using an inexpensive hot-air station and a skillet.  Approximately 180 x 0.6mm balls.  A stencil for placing the balls is absolutely required.  In my experience, the difficult part is removing and cleaning the board/chip.  Obviously, that wouldn't be a part of what you intend to do, so yield would be better.  Any board that I've ruined has always been ruined in the removal step.

If I was to do a one off board as you're trying to do, I'd have at least one extra PCB made.  Depending on the cost of the FPGA, I might order a backup of the chip as well.

As for alignment, that was my biggest concern starting out.  It turns out that alignment is very easy. As long as it is close and the heat from the gun is even (i.e. all the solder balls melt at the same time), it will self align.  It's very cool to watch.

While it can definitely be done by hand, I'd still put considerable effort into finding a pre-assembled board that fit my requirements before I tried to roll my own.

- Nate

2011\05\08@112841 by Oli Glaser

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On 08/05/2011 16:07, Mike Harrison wrote:
> On Sun, 08 May 2011 15:46:28 +0100, you wrote:
>
>> On 08/05/2011 15:13, V G wrote:
>>> On Sun, May 8, 2011 at 9:55 AM, Bob Ammerman<EraseMErvammermanspam_OUTspamTakeThisOuTroadrunner.com>   wrote:
>>>> Any decent size BGA is not going to work on a 2-layer board.
>>> I'm thinking between 100 and 200 pins. So it needs to be 4 layer?
>> At the very least - I made a 2-layer test board for a 64 pin FPGA that
>> "worked", but for any serious use you need power and ground planes for
>> decoupling and controlled impedance purposes, plus the extra routing
>> space. Look into high speed digital techniques and you will see why all
>> this is necessary. Xilinx should have some relevant documentation on
>> their site, about the optimum setup for their chips, how many IOs can
>> switch at once, thermal considerations, etc.
> QFP packaged FPGAs, however are entirely viable on 2 layers, as long as you only have one I/O
> voltage, as this can be on a top-side plane under the chip.

Yes, the board I mention (plus a couple of others, all QFP packages on 2 layers) worked fine, just not at the highest speeds.

2011\05\08@113440 by Oli Glaser

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On 08/05/2011 16:09, V G wrote:
> On Sun, May 8, 2011 at 10:46 AM, Oli Glaser<oli.glaserspamspam_OUTtalktalk.net>  wrote:
>> At the very least - I made a 2-layer test board for a 64 pin FPGA that
>> "worked", but for any serious use you need power and ground planes for
>> decoupling and controlled impedance purposes, plus the extra routing
>> space. Look into high speed digital techniques and you will see why all
>> this is necessary. Xilinx should have some relevant documentation on
>> their site, about the optimum setup for their chips, how many IOs can
>> switch at once, thermal considerations, etc.
> Looks like I need a degree in EE.
>
> I'll go sit in the EE lectures at my university in my spare time next
> year. This looks like some serious stuff.

Didn't mean to put you off, it's not too difficult if you do some reading before hand. If you are not intending to push them to the limits then you can get away with a lot more, and a 2 layer board might be okay. Most of my work with FPGAs has been at high speeds (core and I/O) so I have seen the effects of an unsuitable board.
Best way to find out and learn is just to jump in a try it, it won't seem so bad when you get going. I would maybe select a TQFP package to make life easier on yourself, but a BGA is certainly possible with various techniques documented all over the web.

2011\05\08@113617 by V G

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On Sun, May 8, 2011 at 11:28 AM, Oli Glaser <@spam@oli.glaserKILLspamspamtalktalk.net> wrote:
> On 08/05/2011 16:07, Mike Harrison wrote:
>> On Sun, 08 May 2011 15:46:28 +0100, you wrote:
>>
>>> On 08/05/2011 15:13, V G wrote:
>>>> On Sun, May 8, 2011 at 9:55 AM, Bob Ammerman<KILLspamrvammermanKILLspamspamroadrunner.com>   wrote:
>>>>> Any decent size BGA is not going to work on a 2-layer board.
>>>> I'm thinking between 100 and 200 pins. So it needs to be 4 layer?
>>> At the very least - I made a 2-layer test board for a 64 pin FPGA that
>>> "worked", but for any serious use you need power and ground planes for
>>> decoupling and controlled impedance purposes, plus the extra routing
>>> space. Look into high speed digital techniques and you will see why all
>>> this is necessary. Xilinx should have some relevant documentation on
>>> their site, about the optimum setup for their chips, how many IOs can
>>> switch at once, thermal considerations, etc.
>> QFP packaged FPGAs, however are entirely viable on 2 layers, as long as you only have one I/O
>> voltage, as this can be on a top-side plane under the chip.
>
> Yes, the board I mention (plus a couple of others, all QFP packages on 2
> layers) worked fine, just not at the highest speeds.

QFP it is, then!


'[EE] Soldering BGA'
2011\10\14@192916 by V G
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So it seems that I have to use this
BGA<www.micron.com/products/ProductDetails.html?product=products/dram/psram-cellularram/MT45W8MW16BGX-701+IT>part
(can't find it in any other package). How would I go about soldering
it? Just place it on the PCB and stick it in the oven? My biggest concern is
the positioning of the part on the pads. How would I know that it's aligned
properly? How perfect does the aligning have to be

2011\10\14@195608 by peter green

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V G wrote:
> So it seems that I have to use this
> BGA<www.micron.com/products/ProductDetails.html?product=products/dram/psram-cellularram/MT45W8MW16BGX-701+IT>part
> (can't find it in any other package). How would I go about soldering
> it? Just place it on the PCB and stick it in the oven? My biggest concern is
> the positioning of the part on the pads. How would I know that it's aligned
> properly? How perfect does the aligning have to be?
>   Afaict the aligning doesn't have to be perfect, the surface tension of the balls will snap it into place if it's slightly off. The problem comes if it's sufficiantly far off that it snaps to a 1 ball offset rather than snapping to the correct position or if it decides to solder itself to the vias instead of the pads (see below).

If there is going to be a grid of vias under the BGA connected to the grid of pads via 45 degree tracks it is strongly advisable to set up your PCB package to cover the vias in soldermask. Another option is to put the vias in the pads themselves but if you do this then those vias need to be filled with solid copper which will increase your PCB fabrication cost (given how fine this BGA is though you may have little choice but to go for vias in pads).

2011\10\14@205128 by V G

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On Fri, Oct 14, 2011 at 7:56 PM, peter green <RemoveMEplugwashTakeThisOuTspamp10link.net> wrote:

> If there is going to be a grid of vias under the BGA connected to the
> grid of pads via 45 degree tracks it is strongly advisable to set up
> your PCB package to cover the vias in soldermask. Another option is to
> put the vias in the pads themselves but if you do this then those vias
> need to be filled with solid copper which will increase your PCB
> fabrication cost (given how fine this BGA is though you may have little
> choice but to go for vias in pads).
>
>
SIGH. The package is a 9x6 BGA and the ball pitch is 0.75mm. This is going
to be very difficult to design.

Looks like I'll have to go with DRAM in TSSOP. BGA looks too hard to design..
It'll probably end up being unroutable on 2 layers

2011\10\14@210503 by Bob Blick

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On Friday, October 14, 2011 8:41 PM, "V G" <spamBeGonex.solarwind.xspamBeGonespamgmail.com>
wrote:

> SIGH. The package is a 9x6 BGA and the ball pitch is 0.75mm. This is
> going
> to be very difficult to design.

Ouch. 0.75mm is what I would consider micro-BGA, and not anything I
would consider (at this date) possible to prototype with "in house".

Bob
-- http://www.fastmail.fm - Or how I learned to stop worrying and
                         love email again

2011\10\14@212345 by V G

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On Fri, Oct 14, 2011 at 9:05 PM, Bob Blick <TakeThisOuTbobblickEraseMEspamspam_OUTftml.net> wrote:

> On Friday, October 14, 2011 8:41 PM, "V G" <RemoveMEx.solarwind.xspamTakeThisOuTgmail.com>
> wrote:
>
> > SIGH. The package is a 9x6 BGA and the ball pitch is 0.75mm. This is
> > going
> > to be very difficult to design.
>
> Ouch. 0.75mm is what I would consider micro-BGA, and not anything I
> would consider (at this date) possible to prototype with "in house".
>

I need /some/ way to add memory to my FPGA. SRAM is wayyy too expensive in
the megabit range, DRAM is hard to use, and the cellularRAM by Micron is in
a very small and almost impossible to prototype package. The only realistic
option I have here is the TSSOP DRAM.

I know Xilinx's software generates DRAM controllers, but I've never done it
before and I don't know how exactly this will all fit together with the
TSSOP DRAMs I'm currently browsing at Mouser.

DRAMs:
http://nz.mouser.com/Semiconductors/Integrated-Circuits-ICs/Memory/DRAM/_/N-6j75u?P=1z0xts6Z1z0y15pZ1z0xz7wZ1z0xttdZ1z0xtrtZ1yzt5m8Z1z0y16jZ1yzuykwZ1z0w6vwZ1z0sr05Z1z0w6phZ1z0sr02Z1z0w6qiZ1z0w0i3

The specs on the DRAMs look very attractive, including the speed. But I'm
feeling uneasy. I just need someone to say "hey don't worry man, the Xilinx
memory controller generator will work nicely with those DRAMs and you'll be
reading and writing in no time"

2011\10\15@004316 by Jesse Lackey

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This may be a dumb suggestion, but why not use some regular computer laptop/desktop SDRAM in a SIMM module?  It could be older very generic stuff that sure seems likely to be supported by xilinx's software. Physically too big?

You could ask on a xilinx forum about the DRAMs from mouser, you'd be much more likely to find that guy that knows it will work.

Good luck!
J

V G wrote:
{Quote hidden}

> reading and writing in no time"

2011\10\15@010435 by V G

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On Sat, Oct 15, 2011 at 12:43 AM, Jesse Lackey <RemoveMEjsl-mlEraseMEspamEraseMEcelestialaudio.com>wrote:

> This may be a dumb suggestion, but why not use some regular computer
> laptop/desktop SDRAM in a SIMM module?  It could be older very generic
> stuff that sure seems likely to be supported by xilinx's software.
> Physically too big?
>
> You could ask on a xilinx forum about the DRAMs from mouser, you'd be
> much more likely to find that guy that knows it will work.
>
>
I like the parallel processing of FPGAs

2011\10\15@011815 by V G

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On Sat, Oct 15, 2011 at 1:04 AM, V G <RemoveMEx.solarwind.xspam_OUTspamKILLspamgmail.com> wrote:

> On Sat, Oct 15, 2011 at 12:43 AM, Jesse Lackey <RemoveMEjsl-mlTakeThisOuTspamspamcelestialaudio.com>wrote:
>
>> This may be a dumb suggestion, but why not use some regular computer
>> laptop/desktop SDRAM in a SIMM module?  It could be older very generic
>> stuff that sure seems likely to be supported by xilinx's software.
>> Physically too big?
>>
>> You could ask on a xilinx forum about the DRAMs from mouser, you'd be
>> much more likely to find that guy that knows it will work.
>>
>>
> I like the parallel processing of FPGAs.
>

My apologies, misread the reply. Yes, I could use those modules, but they
have LOTS of pins. I'll give it a try though seeing as they're pretty cheap..
Laptop DDR seems like a good place to start

2011\10\15@065359 by fred jones

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Have a look at the dimensions of this chip:
cds.linear.com/docs/Datasheet/1068fb.pdf
I have not looked up yours but based on Bob Blick's response, it looks like is larger than the link I posted.  If that's true, I use this chip and regularly successfully solder it.  I line it up on the pads and hold it in place with a tool in one hand.  I get a tinned soldering iron and touch a few pins to tack it down.  Then I get the soldering iron and solder and I "blob" solder along the row of pins on the opposite side.  Once finished I do the same on the side I tacked down.  At this point all pins are covered in a bead of solder.  Next I get desoldering braid and I suck the solder up.  This removes most of the solder including any connections between adjacent pins leaving only a little solder under each pin to the pad.  I also do this with the Philips LPC2148 ARM processors.
http://ics.nxp.com/products/lpc2000/lpc214x/
It's hard psychologically the first time you do it, but after you see how easy it is and see it work, no problem.  I very rarely have an issue doing it this way.  The only problem I have had is not a short between pins/pads but one that isn't making electrical connection to a pad.  This has happened only twice and was fixed by touching the pad with the soldering iron to reheat.  And this is very rare.
Good luck,
FJ

{Quote hidden}

> -

2011\10\15@081257 by Oli Glaser

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On 15/10/2011 11:53, fred jones wrote:
> Have a look at the dimensions of this chip:
> cds.linear.com/docs/Datasheet/1068fb.pdf
> I have not looked up yours but based on Bob Blick's response, it looks like is larger than the link I posted.  If that's true, I use this chip and regularly successfully solder it.

I may have missed something here, but that link is to an SSOP package, whilst the thread seems to be about BGA packages (i.e. pads underneath the chip as opposed to on the sides)

2011\10\15@131647 by V G

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On Sat, Oct 15, 2011 at 8:12 AM, Oli Glaser <spamBeGoneoli.glaserSTOPspamspamEraseMEtalktalk.net> wrote:

> On 15/10/2011 11:53, fred jones wrote:
> > Have a look at the dimensions of this chip:
> > cds.linear.com/docs/Datasheet/1068fb.pdf
> > I have not looked up yours but based on Bob Blick's response, it looks
> like is larger than the link I posted.  If that's true, I use this chip and
> regularly successfully solder it.
>
> I may have missed something here, but that link is to an SSOP package,
> whilst the thread seems to be about BGA packages (i.e. pads underneath
> the chip as opposed to on the sides)
>
>

Same confusion I'm having. Can't stick a soldering iron under a BGA package..
Best thing I can do is align with silkscreen. Anyway, I'm switching to
Micron DRAM TSSOP chips. It seems the MIG explicity states they support
those particular parts and they're only $10 or so for 256 mbit

2011\10\15@141122 by Dwayne Reid

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At 11:04 PM 10/14/2011, V G wrote:
>On Sat, Oct 15, 2011 at 12:43 AM, Jesse Lackey
><KILLspamjsl-mlspamBeGonespamcelestialaudio.com>wrote:
>
> > This may be a dumb suggestion, but why not use some regular computer
> > laptop/desktop SDRAM in a SIMM module?  It could be older very generic
> > stuff that sure seems likely to be supported by xilinx's software.
> > Physically too big?
> >
> > You could ask on a xilinx forum about the DRAMs from mouser, you'd be
> > much more likely to find that guy that knows it will work.
> >
> >
>I like the parallel processing of FPGAs.

I guess that I just became extremely confused.  Sort of like . . . HUH ?!?

What does using or not using SIMM SDRAM have to do with parallel processing?  I *think* that those old SIMMs are 16 bits wide (18 bits if they have parity).

You could also use the cache RAM from really old computer mother-boards.

I'm not trying to start a confrontation - I'm genuinely confused.  Can you explain?

dwayne

-- Dwayne Reid   <EraseMEdwaynerspamEraseMEplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax
http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

2011\10\15@144534 by V G

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On Sat, Oct 15, 2011 at 2:11 PM, Dwayne Reid <@spam@dwayner@spam@spamspam_OUTplanet.eon.net> wrote:

>  I guess that I just became extremely confused.  Sort of like . . . HUH
> ?!?
>
> What does using or not using SIMM SDRAM have to do with parallel
> processing?  I *think* that those old SIMMs are 16 bits wide (18 bits
> if they have parity).
>
> You could also use the cache RAM from really old computer mother-boards.
>
> I'm not trying to start a confrontation - I'm genuinely
> confused.  Can you explain?
>
>
It seems some of my emails are going through and some are not. Not sure
what's going on here.

I misread his reply (it was late and I was tired). I thought he was telling
me to use a computer or CPU or whatever. I misread it.


My apologies, misread the reply. Yes, I could use those modules, but they
> have LOTS of pins. I'll give it a try though seeing as they're pretty cheap.
> Laptop DDR seems like a good place to start.



Anyway, I found that Xilinx's MIG supports (explicitly stated) the Micron
SDRAM TSSOP modules. I'll be using those and see how it goes. They're cheap,
fast, and easy to solder. Hope this works out.

If I need high throughput, I'll cache the data on the FPGA's block RAM/flip
flops/whatever, split the data up into equal sized parts (let's say 4 parts
per burst if I need 4x the throughput) and write it simultaneously (in
parallel) to 4 modules at the same time. So DRAM module 1 would contain part
1 of the data, module 2 would contain part two of the data, etc. But I
highly doubt I'll need that since these modules have 5ns delay and are more
than fast enough to start with

2011\10\16@121036 by Electron

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At 01.56 2011.10.15, you wrote:
{Quote hidden}

By the way do BGA's require solder on the PCB pads? If I'm not mistaken
those BGA balls are already exactly that: solder.

2011\10\16@160334 by Jim Franklin

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The PCB doesn't need solder, as you say, the balls ARE solder.
*I just "broke" a template, so I manually placed 100+ 0.5mm balls on a chip
using a pin and a microscope.. it CAN be done, but it SHOULDN'T be done!

-Jim

{Original Message removed}

2011\10\16@163534 by V G

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On Sun, Oct 16, 2011 at 4:03 PM, Jim Franklin <spamBeGonejimfranklinspamKILLspamtalktalk.net>wrote:

> The PCB doesn't need solder, as you say, the balls ARE solder.
> *I just "broke" a template, so I manually placed 100+ 0.5mm balls on a chip
> using a pin and a microscope.. it CAN be done, but it SHOULDN'T be done!
>

It must have been a really expensive chip. What was it

2011\10\17@154229 by Jim Franklin

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It was only an AMD graphics chip on a laptop.. but I was determined to win.
(and I did).

I only did it manually due to the busted template, I have a shiny new
microscope, and a free afternoon. And it's good practice.

-Jim



{Original Message removed}

2011\10\17@155754 by V G

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On Mon, Oct 17, 2011 at 3:42 PM, Jim Franklin <.....jimfranklinspam_OUTspamtalktalk.net>wrote:

> It was only an AMD graphics chip on a laptop.. but I was determined to win.
> (and I did).
>
> I only did it manually due to the busted template, I have a shiny new
> microscope, and a free afternoon. And it's good practice.
>

Wow nice. What was wrong with the chip? Why was the reason for removing it
and reballing it?

Also, my biggest problem with these thing BGA chips is designing the PCB and
routing it. I can't go more than 2 layers or with fancy things like vias in
pads or ill get expensive. I have to stick with surface mount leaded
components only :

2011\10\17@162726 by M.L.

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On Mon, Oct 17, 2011 at 3:57 PM, V G <TakeThisOuTx.solarwind.x.....spamTakeThisOuTgmail.com> wrote:
> Also, my biggest problem with these thing BGA chips is designing the PCB and
> routing it. I can't go more than 2 layers or with fancy things like vias in
> pads or ill get expensive. I have to stick with surface mount leaded
> components only :(

You need 4 layers minimum and filled micro vias if you're going to do
fine pitch BGA correctly. Yes, there may be other methods.

6 or many more layers for larger devices.

-- Martin K

2011\10\17@163700 by V G

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On Mon, Oct 17, 2011 at 4:26 PM, M.L. <TakeThisOuTmKILLspamspamspamlkeng.net> wrote:

>  You need 4 layers minimum and filled micro vias if you're going to do
> fine pitch BGA correctly. Yes, there may be other methods.
>
> 6 or many more layers for larger devices.
>

Yeah :( The Nexys 2 board that I have, which uses the same Micron pSRAM chip
that i was looking at, uses 4 layers, consisting of 2 signal layers and 2
power layers. I don't know exactly what kind of vias they're using.

I'm not going to mess around with BGA until I find some poor prof's funds
for which I can use to make multi layer PCBs, with fancy vias and stuff.
(jkjk

2011\10\17@171105 by Jim Franklin

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It's a common fault on some of the laptops, the GFX chip has no additional
cooling and lead-free solder balls have a habit of developing fractures when
stressed.

(old XBOX 360's (Red ring of death) and PS3's (Yellow light of death) have
similar problems)


{Original Message removed}

2011\10\17@174524 by Electron

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This RoHS thing seems to exist only to cause huge reliability problems. :-/

By the way what is the punishment if a small company (I don't mean Swatch :D )
gets caught using non-RoHS compliant solder? Ball-cutting? Death penalty? Or? =8-I


At 23.11 2011.10.17, you wrote:
>It's a common fault on some of the laptops, the GFX chip has no additional
>cooling and lead-free solder balls have a habit of developing fractures when
>stressed.
>
>(old XBOX 360's (Red ring of death) and PS3's (Yellow light of death) have
>similar problems)
>
>
>{Original Message removed}

2011\10\17@183017 by M.L.

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On Mon, Oct 17, 2011 at 5:11 PM, Jim Franklin <.....jimfranklinspamRemoveMEtalktalk.net> wrote:
> It's a common fault on some of the laptops, the GFX chip has no additional
> cooling and lead-free solder balls have a habit of developing fractures when
> stressed.
>
> (old XBOX 360's (Red ring of death) and PS3's (Yellow light of death) have
> similar problems)
>

That might be what happened to my last WiFi router. It was acting
flaky - dropping packets, rebooting.
I took it apart and the chip had overheated for so long that the back
side of the PCB which should have been green had turned yellow.
I'd like to think they didn't design it to fail in slightly more than
2 years, but I suspect they knew pretty well about how long it would
live at room temperature.

-- Martin K

2011\10\17@185511 by V G

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On Mon, Oct 17, 2011 at 5:44 PM, Electron <RemoveMEelectron2k4spamspamBeGoneinfinito.it> wrote:

> This RoHS thing seems to exist only to cause huge reliability problems. :-/
>

Health, safety, environment

2011\10\18@040715 by Jake Anderson

flavicon
face
On 10/18/2011 09:54 AM, V G wrote:
> On Mon, Oct 17, 2011 at 5:44 PM, Electron<spamBeGoneelectron2k4@spam@spamspam_OUTinfinito.it>  wrote:
>
>> This RoHS thing seems to exist only to cause huge reliability problems. :-/
>>
> Health, safety, environment.
I'm sure the environment is thanking us for all the mining and landfill we are doing now due to ROHS causing electronics to suck so as to avoid putting that small amount of well encapsulated lead into landfills.

2011\10\18@052257 by Wouter van Ooijen

face picon face
>> This RoHS thing seems to exist only to cause huge reliability problems. :-/
> Health, safety, environment.

But lead-acid car batteries are still allowed? I am a stout environmentalist, but banning lead solder while allowing lead car batteries seems ridiculous to me.

--
Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu

2011\10\18@074627 by M.L.

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face
On Tue, Oct 18, 2011 at 5:22 AM, Wouter van Ooijen <TakeThisOuTwouterspamspamvoti.nl> wrote:
> But lead-acid car batteries are still allowed? I am a stout
> environmentalist, but banning lead solder while allowing lead car
> batteries seems ridiculous to me.
>

Nearly 100% of car batteries are recycled. Lead is a valuable mineral,
but it's made difficult to recover when alloyed and spread out all
over a PCB. A lead/antimony car battery can be relatively simple to
recycle.

I don't know for sure, but as an example I don't think many cell
phones would end up being recycled.

-- Martin K

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