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'[EE] Parallel passives and sprinkled vias?'
2010\08\29@114536 by Nathan Nottingham

picon face

Being self-taught for what it's worth, I really enjoy looking at other's schematics and PCB designs and trying to understand why things are done the way the are.  Amongst many things, there are two common designs I see that I don't understand:

Parallel caps:   one schematic I recently saw placed eight 1uf caps together.  All tied to +V and GND and nothing else in their own separate block on the schematic.  Couldn't this be replaced with a single 8uf cap?  Other caps can be found throughout the design that simply connect between +V and GND..  Why no replace them all with a single cap of the sum value?  Same design has a 1uf and .1uf cap in parallel in other places but not necessarily directly between +V and GND.  Replace with 1.1uf to reduce parts count?

Another thing I see commonly, are GND vias sprinkled all over the PCB.  Any rhyme or reason for this?

Thanks,
Nat

2010\08\29@125054 by Michael Watterson

face picon face
 On 29/08/2010 16:45, Nathan Nottingham wrote:
> Being self-taught for what it's worth, I really enjoy looking at other's schematics and PCB designs and trying to understand why things are done the way the are.  Amongst many things, there are two common designs I see that I don't understand:
>
> Parallel caps:   one schematic I recently saw placed eight 1uf caps together.  All tied to +V and GND and nothing else in their own separate block on the schematic.  Couldn't this be replaced with a single 8uf cap?  Other caps can be found throughout the design that simply connect between +V and GND.  Why no replace them all with a single cap of the sum value?  Same design has a 1uf and .1uf cap in parallel in other places but not necessarily directly between +V and GND.  Replace with 1.1uf to reduce parts count?
>
> Another thing I see commonly, are GND vias sprinkled all over the PCB.  Any rhyme or reason for this?
>
> Thanks,
> Nate
The caps are in reality close to each IC to stop "noise" from IC on power rails (simple easy to understand "lie". The real physics is a little more complex).

A track has inductance. Typically on RF you need a very short connection to "ground" and so the "Ground" is usually a dedicated layer. Digital is RF, really.


A 1uF might have higher ESR or inductance than a 10nF or 100nF. Some designs you can indeed use a single 1uF ceramic. That might be more expensive than a  cheap 1uF electrolytic and 10nF ceramic.

If you think "ordinary" designs are odd, you should see some 10GHz etc. a via every few mm on a ground track to a ground plane as 3cm of track with via each end to ground is an aerial :-)

2010\08\29@125129 by Alex Harford

face picon face
On Sun, Aug 29, 2010 at 8:45 AM, Nathan Nottingham
<spam_OUTkphlightTakeThisOuTspamnottingham-tech.com> wrote:
>
> Being self-taught for what it's worth, I really enjoy looking at other's schematics and PCB designs and trying to understand why things are done the way the are.  Amongst many things, there are two common designs I see that I don't understand:
>
> Parallel caps:   one schematic I recently saw placed eight 1uf caps together.  All tied to +V and GND and nothing else in their own separate block on the schematic.  Couldn't this be replaced with a single 8uf cap?  Other caps can be found throughout the design that simply connect between +V and GND.  Why no replace them all with a single cap of the sum value?  Same design has a 1uf and .1uf cap in parallel in other places but not necessarily directly between +V and GND.  Replace with 1.1uf to reduce parts count?

These are probably decoupling caps, and must be placed as close to the
chip as possible.  Generally in schematics they are all grouped
together on one page for readability, but that it *not* where they are
laid out on the PCB.

Not sure about the 1uF and 0.1uF, can you provide a link to an example
schematic?

2010\08\29@125724 by Thomas Sefranek

picon face

On Aug 29, 2010, at 11:45 AM, Nathan Nottingham wrote:

>
> Being self-taught for what it's worth, I really enjoy looking at other's schematics and PCB designs and trying to understand why things are done the way the are.

Great!  I also had an idiot for an instructor before I got my degree.

>  Amongst many things, there are two common designs I see that I don't understand:
>
> Parallel caps:   one schematic I recently saw placed eight 1uf caps together.

>  All tied to +V and GND and nothing else in their own separate block on the schematic.

Usually it is a schematic art-in-fact to lump the bypass caps.
I try to associate them with each device I intend to bypass.

>  Couldn't this be replaced with a single 8uf cap?

Not if they are bypassing several devices.

>  Other caps can be found throughout the design that simply connect between +V and GND.  Why no replace them all with a single cap of the sum value?

>  Same design has a 1uf and .1uf cap in parallel in other places but not necessarily directly between +V and GND.  Replace with 1.1uf to reduce parts count?

Often a bulk bypass (large value caps) can not bypass very high frequencies because of their inductance.
So Low frequencies are bypassed by high value caps, and high frequencies are bypassed by low value caps.
>
> Another thing I see commonly, are GND vias sprinkled all over the PCB.  Any rhyme or reason for this?

Current distribution to allow lower impedances.
>
> Thanks,
> Nate
> -

2010\08\29@132104 by Olin Lathrop

face picon face
Michael Watterson wrote:
> The caps are in reality close to each IC to stop "noise" from IC on
> power rails (simple easy to understand "lie". The real physics is a
> little more complex).

That's a secondary purpose of bypass caps.  The main function is to keep the
power voltage at the IC steady despite large steps in its current demand.
The power feed at the IC may have suitable low impedence at low frequencies,
but usually not low enough impedence at high frequencies due to the
inductance of the feed lines.  A bypass cap is there specifically to provide
the low impedence at the high frequencies that the power feed can't handle
on its own.  Since the leads between the cap and IC also have inductance,
they must be kept as short as possible.  This is why you see a separate
bypass cap at each IC instead of the same total capacitance in one lump
elsewhere.

Sometime people get lazy and put all the bypass caps in one place in the
schematic, although they are actually distributed at each IC.  This is bad
practice unless you at least indicate which IC which bypass cap is for.

> A 1uF might have higher ESR or inductance than a 10nF or 100nF. Some
> designs you can indeed use a single 1uF ceramic.

ESR isn't a issue for ceramic bypass caps.  They all have such low ESR that
it is irrelevant.  The important attribute is the high frequency response.
Above some frequency, the cap no longer works like a cap.

Modern suface mount 1uF caps have better high frequency properties than the
leaded 100nF caps of the last century.  For most "normal" designs you find
around a PIC, 1uF SMD caps are fine for bypassing.

100nF and lower can still have better high frequency performance, so if
you're doing something with deliberate frequecies above 50MHz or so, you
need to look at the capacitor datasheet carefully.  In one design that did
434MHz RF, I ended up using a specific model of 100pF caps because it had
the lowest impedence at 434MHz.

> That might be more
> expensive than a  cheap 1uF electrolytic and 10nF ceramic.

Nonsense.  First, most low voltage ceramic SMD caps up to around 1uF are
about the same price.  Second, they are all cheaper than any electrolytic,
and far more robust with better properties for bypassing.  Electrolytics
have a relatively high ESR and poor high frequency performance, making them
unsuitable for bypass use.

> If you think "ordinary" designs are odd, you should see some 10GHz

Yes, the laws of physics break down above a few GHz after which magic
dominates ;-)


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\29@132338 by Olin Lathrop

face picon face
Alex Harford wrote:
> These are probably decoupling caps, and must be placed as close to the
> chip as possible.  Generally in schematics they are all grouped
> together on one page for readability,

Speak for yourself.  Not on my schematics.

> Not sure about the 1uF and 0.1uF,

The 100nF provides the good high frequency response, and the 1uF a little
more overall capacitance at a little lower frequencies.  Again, for most
common PIC circuits, a single 1uF SMD ceramic close to the PIC leads is
fine.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\29@135234 by Michael Watterson

face picon face
 On 29/08/2010 18:21, Olin Lathrop wrote:
>
> 100nF and lower can still have better high frequency performance, so if
> you're doing something with deliberate frequecies above 50MHz or so, you
> need to look at the capacitor datasheet carefully.  In one design that did
> 434MHz RF, I ended up using a specific model of 100pF caps because it had
> the lowest impedence at 434MHz.
>
>> That might be more
>> expensive than a  cheap 1uF electrolytic and 10nF ceramic.
> Nonsense.  First, most low voltage ceramic SMD caps up to around 1uF are
> about the same price.  Second, they are all cheaper than any electrolytic,
> and far more robust with better properties for bypassing.  Electrolytics
> have a relatively high ESR and poor high frequency performance, making them
> unsuitable for bypass use.000.
I was thinking 50V caps. I work with some 24V radios (About 29V on charge)
Also what is in a new design isn't the same as 30 years ago when SMD was rare.

I'd buy some 50V 1uF ceramic SMD if they were cheap.

2010\08\29@135601 by Michael Watterson

face picon face
 On 29/08/2010 18:24, Olin Lathrop wrote:
> Alex Harford wrote:
>> These are probably decoupling caps, and must be placed as close to the
>> chip as possible.  Generally in schematics they are all grouped
>> together on one page for readability,
> Speak for yourself.  Not on my schematics.
I dislike that and regard it as laziness. I also put the cap on the schematic roughly where it goes. I try to do schematic as I might want to layout the board.

It helps fault finding and repair too if a schematic has some topological similarity to the real PCBs.
>> Not sure about the 1uF and 0.1uF,
> The 100nF provides the good high frequency response, and the 1uF a little
> more overall capacitance at a little lower frequencies.  Again, for most
> common PIC circuits, a single 1uF SMD ceramic close to the PIC leads is
> fine.
Though this is  PIC list, the OP didn't mention PICs

2010\08\29@135801 by Michael Watterson

face picon face
 On 29/08/2010 18:21, Olin Lathrop wrote:
> Michael Watterson wrote:
>> The caps are in reality close to each IC to stop "noise" from IC on
>> power rails (simple easy to understand "lie". The real physics is a
>> little more complex).
> That's a secondary purpose of bypass caps.  The main function is to keep the
> power voltage at the IC steady despite large steps in its current demand.
> The power feed at the IC may have suitable low impedence at low frequencies,
> but usually not low enough impedence at high frequencies due to the
> inductance of the feed lines.  A bypass cap is there specifically to provide
> the low impedence at the high frequencies that the power feed can't handle
> on its own.  Since the leads between the cap and IC also have inductance,
> they must be kept as short as possible.  This is why you see a separate
> bypass cap at each IC instead of the same total capacitance in one lump
> elsewhere.
That's simply a different more long winded way of saying what I had admitted was simplified (as the OP obviously was a little bewildered already or would not have asked)

2010\08\29@151644 by Olin Lathrop

face picon face
Michael Watterson wrote:
>>> The caps are in reality close to each IC to stop "noise" from IC on
>>> power rails (simple easy to understand "lie". The real physics is a
>>> little more complex).
>> That's a secondary purpose of bypass caps.  The main function is to
>> keep the power voltage at the IC steady despite large steps in its
>> current demand. The power feed at the IC may have suitable low
>> impedence at low frequencies, but usually not low enough impedence
>> at high frequencies due to the inductance of the feed lines.  A
>> bypass cap is there specifically to provide the low impedence at the
>> high frequencies that the power feed can't handle on its own.  Since
>> the leads between the cap and IC also have inductance, they must be
>> kept as short as possible.  This is why you see a separate bypass
>> cap at each IC instead of the same total capacitance in one lump
>> elsewhere.
> That's simply a different more long winded way of saying what I had
> admitted was simplified (as the OP obviously was a little bewildered
> already or would not have asked).

By the way, when you quote others' messages, the blank lines are squashed
out making it difficult to read.  The blank line after the quoted part and
your response also seems to get squashed somewhere.  You might want to look
at that.  What is quoted above is how I received your message.  I left it
unfixed this time so you could see what it looks like.

Anyway, my point was that bypass caps are primarily for holding the power
voltage at the part, not for protecting the rest of the power net from high
frequency glitches caused by the part (they have that effect, but that is
not their primary purpose).


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\29@170858 by William \Chops\ Westfield

face picon face

On Aug 29, 2010, at 8:45 AM, Nathan Nottingham wrote:

> GND vias sprinkled all over the PCB.  Any rhyme or reason for this?

An "ideal ground" has exactly the same potential ("0V") everywhere it  connects to anything, and things like ground planes and lots of vias  are attempts to make the actual Ground "more ideal" in spite of the  fact that real PCB traces have resistance, capacitance, and inductance.

I'm not quite sure how this relates to "ground everything to a single  point", which is another recommended practice, except to sort-of  "expand" that "single point" to the whole PCB as much as possible.   When you have to start actually worrying about the single point stuff  seems to be dependent on frequency and size of PCB, and is still  pretty much black magic to me...

The other thing I've learned from looking at other peoples' designs is  that there are an awful lot of "professionally designed and  manufactured" devices that DON'T have "carefully designed" PCBs.   Autoroute and pay a slight bit of attention to wider traces for power,  and "ship it."  They seem to work fine, though.  I guess it's like  using a known-inefficient high-level language; relatively basic  practices take a lot less time and work "well enough", compared to the  high-effort that full attention would have required.  If you can make  it work by adding extra layers with power planes, that ends up being  cheaper (at moderate quantities) than figuring out how to get it  working without the "extra" layers.

BillW

2010\08\29@193001 by RussellMc

face picon face
> Anyway, my point was that bypass caps are primarily for holding the power
> voltage at the part, not for protecting the rest of the power net from high
> frequency glitches caused by the part (they have that effect, but that is
> not their primary purpose).

Also note that the shorter and/or less area in a current carrying loop
the less radiating effect it is liable* to have. A capacitor placed
close to an IC that generates a current spike (source or sink) from
power supply  to/from ground will typically* more readily act as a
short circuit for the spike current AND minimise radiating effects.
You (and Murphy) can produce long paths that have less radiating
effects than short ones, but as a general* rule the shorter the path
the better. An ideal ground plane covering the whole PCB will allow
you to connect to ground at any point BUT as nothing is ideal,
minimising paths as much as possible is usually* wise.  (On actual PCB
layout visualise source and sink points for noise and visualise what
physical paths current will follow. Minimum path length and minimum
loop area are usually* the aim.



  Russell

* - added to acknowledge the effects of deep magic. These statements
usually apply for most values of usually :-)

2010\08\29@193147 by RussellMc

face picon face
>> These are probably decoupling caps, and must be placed as close to the
>> chip as possible.  Generally in schematics they are all grouped
>> together on one page for readability,

> Speak for yourself.  Not on my schematics.

He wasn't intending to speak for himself - he was saying what "Mr
Generally" does.
You'll find that generally Generally does as he says, desirable or not..


    R

2010\08\30@000553 by Marechiare

picon face
> Anyway, my point was that bypass caps are primarily for
> holding the power voltage at the part, not for protecting
> the rest of the power net from high frequency glitches
> caused by the part (they have that effect, but that is not
> their primary purpose).

Some people would say that's real sloppy. A precision analog circuit
would like its ground to be protected from glitches caused by other
parts. And if the primary is precision analog then some people might
think of the protecting to be the primary purpose

2010\08\30@011415 by Justin Richards

face picon face
While on the topic of Circuit Boards, I have seen many boards with 94V
on the component site.

Currently I have in front of me a graphical LCD display with A1 94V-0
in the top left corner.

I have seen this on many boards inside DVD players, CD players, Video
player TV's etc.

Long ago I drew the conclusion that it is not related to supply volts.

Any clues as to what the 94V is for.

Justi

2010\08\30@013701 by Sean Breheny

face picon face
It stands for UL flammability standard 94. V-0 is the best rating
(self extinguishing within 10 seconds after removal of external heat
source).

See: http://www.rtpcompany.com/info/ul/ul94v012.htm

Sean


On Mon, Aug 30, 2010 at 1:14 AM, Justin Richards
<.....justin.richardsKILLspamspam@spam@gmail.com> wrote:
{Quote hidden}

>

2010\08\30@013847 by Sean Breheny

face picon face
One more note: the fiberglass composite material which makes up modern
circuit boards is often called FR-4. This stands for Flame Retardant
4. I believe that the raw fiberglass material is called G-10 but once
they add the flame retardant chemicals to it, it is called FR-4.

Sean


On Mon, Aug 30, 2010 at 1:37 AM, Sean Breheny <shb7spamKILLspamcornell.edu> wrote:
{Quote hidden}

>> -

2010\08\30@015725 by RussellMc

face picon face
> One more note: the fiberglass composite material which makes up modern
> circuit boards is often called FR-4. This stands for Flame Retardant
> 4. I believe that the raw fiberglass material is called G-10 but once
> they add the flame retardant chemicals to it, it is called FR-4.

Pretty much.
AIUI G-10 and FR4 use a different epoxy and G10 is mechanically
slightly superior to FR4 but FR4 is now almost exclusively used in
preference.
Both use a woven fibreglass material. (The fire retardation works by
incorporating bromides in the material which release Bromine at
combustion temperatures.

Quoting a PCB FAQ:  There are red and blue logos. Red is UL94-V0, blue
is UL94-HB. If you have a blue logo material, it is either XPC
(phenolic) or G10 (glass epoxy). In 1.50/1.60mm FR4 the logo is in the
middle layer (layer 4) of the common 8 layer construction. ie your
logo should be red if you think you have a fire extinguishing board. .

I wrote the following for  another thread a few days ago and decided
not to send it. Now seems a good time to use it :-)
__________

FR2 is paper with phenolic resin. Your standard cheap junk rubbish
boards. Punching (or using at all) not recommended. Beloved of Asian
manufacturers aiming at low cost. Nasty ability to split and radiate
cracks which may break copper tracks.

FR3 is essentially FR2 with epoxy rather than phenolic resin - still
paper. Good "punchability"
__________

FR4 is essentially glass - epoxy resin laminate.with bromides
incorporated to provide self extinguishing properties.
Usually routed rather than punched.

CEM3 (more Japan and some other Asia) is glass-epoxy but instead of a
woven fabric as in FR4 uses random non woven glass fibres. Instantly
distinguishable by its white colour. Equally as good as FR4.

G10 (often seen in older specs is glass-epoxy, different epoxy to FR4
and not flame retardant. Claimed more punchable than FR4 - not obvious
why.



          Russell McMaho

2010\08\30@030413 by Ruben Jönsson

flavicon
face
> Anyway, my point was that bypass caps are primarily for holding the power
> voltage at the part, not for protecting the rest of the power net from high
> frequency glitches caused by the part (they have that effect, but that is
> not their primary purpose).
>
>
I would say that their primary purpose is to operate as a reservoir for short term current surges in the parts they are connected to. If they are connected in the correct way (as close to the part as possible with short, low impedance tracks (thick)) and if they have low ESR for high frequencies they will have the following effects:

* The power voltage of the part is kept at a steady, stable level.

* The current loop caused by the surge is kept very close to the IC responisble for the surge and by doing so the voltage on the rest of the power net is also kept at a steady, stable level.
* Since the current loop is kept very small, the resulting conducted and radiated EMI can also be kept at a very low level (if rating these effects, I would say that this is the primary one).

When laying out bypas caps for an IC, I try to visualize how the current surges from the IC will flow in the circuit and keep those currents as close to the IC as possible. This always includes a very good ground plane and perhaps more than one via from the negative side of the cap to that ground plane. While keeping the ground plane as big and homogeneous as possible, I also try to connect the IC and the cap to the power net in a way that the current for the surge will most likely be drawn from the cap than from the rest of the net (impedance much lower to the cap than the rest of the power net). This can mean that the positive side of the cap will be connected to the power net with a Y (or V) like connection instead of a T with the traces between the IC and the cap much thicker than the traces for the rest of the power net.

Another thing to keep in mind here is that the frequency domain in the current surges from digital circuits (especially high frequency microprocessors where thousands of transistors switch states in each clock cycle) can have very high frequency components which is why it is important to keep the impedance between the IC and the cap very low at those high frequencies.

I have been doing circuit boards for low to medium frequncy (up to around 50MHz) microprocessors for a very long time and following those simple rules mentioned above will almost always produce boards with very low emitted EMI which is very important since all board that will be used and sold professionally will have to be compliant against conducted and radiated EMI standards. Since measuring the radiated EMI is one of the most expensive EMC tests, it is good to keep the test time as short as possible.

/Ruben
==============================
Ruben Jönsson
AB Liros Electronic
Box 9124, 200 39 Malmö, Sweden
TEL INT +46 40142078
FAX INT +46 40947388
EraseMErubenspam_OUTspamTakeThisOuTpp.sbbs.se
==============================

2010\08\30@073955 by Olin Lathrop

face picon face
'William Chops" Westfield ' <westfwspamspam_OUTmac.com wrote:
> If you can make
> it work by adding extra layers with power planes, that ends up being
> cheaper (at moderate quantities) than figuring out how to get it
> working without the "extra" layers.

What I do a lot with 2 layer boards is to try to keep the bottom layer as a
ground plane.  Most of the connections are on the top layer, and the bottom
layer is used sparingly for short "jumpers".

The Eagle autorouter can help with this by setting the cost of running in
the bottom layer high.  Actually I set the cost in polygons high and use a
polygon for the mostly-ground layer.  Unfortunately there is no way to
explain to Eagle that the important criterion is the maximum dimension of
any island it creates in the bottom layer.  It tends to clump the jumpers
together, even with hugging set to 0.  After the autorouter finishes, I
manually move things around a bit to minimize the size of each island.  Lots
of little jumpers isn't so bad as long as the ground can flow around them.
One big jumper however becomes a slot antenna.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\30@075818 by Olin Lathrop

face picon face
RussellMc wrote:
> Also note that the shorter and/or less area in a current carrying loop
> the less radiating effect it is liable* to have. A capacitor placed
> close to an IC that generates a current spike (source or sink) from
> power supply  to/from ground will typically* more readily act as a
> short circuit for the spike current AND minimise radiating effects.
> You (and Murphy) can produce long paths that have less radiating
> effects than short ones, but as a general* rule the shorter the path
> the better. An ideal ground plane covering the whole PCB will allow
> you to connect to ground at any point BUT as nothing is ideal,
> minimising paths as much as possible is usually* wise.  (On actual PCB
> layout visualise source and sink points for noise and visualise what
> physical paths current will follow. Minimum path length and minimum
> loop area are usually* the aim.

Good points.  Furthermore, you should keep the bypass current off the ground
plane.  Ground planes are funny things in that they work better the less you
use them.

Think of every IC as a high frequency current source between supply and
ground.  The bypass cap shunts this high frequency current.  As you say, you
want to keep this loop short, but you also want to keep this current off the
ground plane.  Otherwise the ground plane becomes a patch antenna and the
bypass cap to IC ground lead the feed point.  I try to run a separate ground
and power net for something like a PIC with 1uF bypass caps between these
two nets.  These local power and ground nets have a single connection to the
rest of the boards's power and ground, with a 10uF cap accross the
connection point.  On four layer boards, the local ground net is often a
polygon in layer 2 just below the PIC and its immediate vicinity, like the
crystal, crystal caps, and of course the bypass caps.

And yes, this has been measured to really work.  I once designed the next
rev of a product originally designed by someone that didn't get grounding.
He thought enclosing everything in metal would magically make the emissions
go away.  There are exceptions, particularly in RF, but shields are often
the first refuge of the incompetent.  This guy used 6 layers with the bottom
layer ground, and had a metal shield tied to this layer soldered over the
processor that produced the noise.  This thing barely squeaked by the FCC
emissions test.

My version used a open 4 layer board with layer 3 a pervasive ground plane
and a few local ground areas in layer 2 for the nasty digital parts.  It
beat the FCC limit by over 14dB.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\30@080047 by Olin Lathrop

face picon face
RussellMc wrote:
>> Speak for yourself. Not on my schematics.
>
> He wasn't intending to speak for himself - he was saying what "Mr
> Generally" does.
> You'll find that generally Generally does as he says, desirable or
> not..

I have seen this practise, but I'm not sure it's so common as to be
"generally" done.  "Generally" also makes it sound acceptable, which I
wanted to point is out it's not.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\30@080158 by RussellMc

face picon face
> One big jumper however becomes a slot antenna.

I was going to make a similar observation about slots before I saw
you'd added it at the end  - if the "go" path is on the top layer and
the "return" path is intersected by a break at 90 degrees the return
current must flow "around" the break and you get a radiating slot as
noted. Obviously it's not as clean and simple as that - currents will
be distributed depending on impedance etc but avoiding large
differences in go and between paths is highly desirable. That plus
minimising loop area of the overall current loop.


2010\08\30@080629 by Ruben Jönsson

flavicon
face
> 'William Chops" Westfield ' <@spam@westfwKILLspamspammac.com wrote:
> > If you can make
> > it work by adding extra layers with power planes, that ends up being
> > cheaper (at moderate quantities) than figuring out how to get it
> > working without the "extra" layers.
>
> What I do a lot with 2 layer boards is to try to keep the bottom layer as a
> ground plane.  Most of the connections are on the top layer, and the bottom
> layer is used sparingly for short "jumpers".
>
Yes, this is exactly what I do and it works very well. Often it is surprising how few "jumpers" that are needed. With a surface mounted board the bottom ground plane layer can get very good coverage.

/Ruben
==============================
Ruben Jönsson
AB Liros Electronic
Box 9124, 200 39 Malmö, Sweden
TEL INT +46 40142078
FAX INT +46 40947388
KILLspamrubenKILLspamspampp.sbbs.se
==============================

2010\08\30@081339 by Olin Lathrop

face picon face
Marechiare wrote:
> Some people would say that's real sloppy. A precision analog circuit
> would like its ground to be protected from glitches caused by other
> parts.

If you have a "precision analog circuit", then you most likely shouldn't be
making assumptions about the cleanliness of the board's main supply, and
therefore filter it properly local to the analog circuit.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2010\08\30@162002 by Marechiare

picon face
>> Some people would say that's real sloppy. A precision analog
>> circuit would like its ground to be protected from glitches
>> caused by other parts.
>
> If you have a "precision analog circuit", then you most likely
> shouldn't be making assumptions about the cleanliness of the
> board's main supply, and therefore filter it properly local to the
> analog circuit.

I mentioned ground plane, not a power supply. Digital IC's current
would flow through the ground plane and therefore produce some voltage
distribution picture around analog parts. You don't need much current
through the ground plane to spoil 1V signal measured with 18-bit ADC

2010\08\31@112938 by Herbert Graf

picon face
On Sun, 2010-08-29 at 13:24 -0400, Olin Lathrop wrote:
> Alex Harford wrote:
> > These are probably decoupling caps, and must be placed as close to the
> > chip as possible.  Generally in schematics they are all grouped
> > together on one page for readability,
>
> Speak for yourself.  Not on my schematics.

Perhaps the OP was speaking of cases where you are dealing with massive
parts.

For the FPGAs I use there are ~100 bypass caps of various sizes per
FPGA, all go on one (or sometimes 2) pages of the schematic dedicated to
that purpose.

TTYL

2010\08\31@121205 by Alex Harford

face picon face
On Tue, Aug 31, 2010 at 8:30 AM, Herbert Graf <RemoveMEhkgrafTakeThisOuTspamgmail.com> wrote:
> On Sun, 2010-08-29 at 13:24 -0400, Olin Lathrop wrote:
>> Alex Harford wrote:
>> > These are probably decoupling caps, and must be placed as close to the
>> > chip as possible.  Generally in schematics they are all grouped
>> > together on one page for readability,
>>
>> Speak for yourself.  Not on my schematics.
>
> Perhaps the OP was speaking of cases where you are dealing with massive
> parts.

Ah, I think I see what Olin was getting at, I wasn't clear in my
original post.  I had in mind Herbert's situation with many bypass
caps on one part.  In my case, at my day job, we use a BGA Geode
processor with 481 balls.  It is split across two pages, power and
I/O.  On the power page we have a big square that is just the VDD/VSS
pins, plus the decoupling caps in the remaining whitespace.

I definitely did not mean that you put *every* decoupling cap on the
entire circuit on one page like an appendix, but I see how it could
have been interpreted that way.

Alex

2010\08\31@232359 by Nathan Nottingham

picon face


On Aug 29, 2010, at 10:57 AM, Thomas Sefranek wrote:
> On Aug 29, 2010, at 11:45 AM, Nathan Nottingham wrote:
>> Being self-taught for what it's worth, I really enjoy looking at other's schematics and PCB designs and trying to understand why things are done the way the are.
>
> Great!  I also had an idiot for an instructor before I got my degree.

I gave up on my old instructor and now plan on getting my BS in PICLIST, as there does indeed seem to be a lot of BS on this list.  :)

That said, thank you all for the great discussion.  I basically take Olin's, Russell's, and [many] others comments and copy/paste what I don't understand into Google.  

For those that asked, the schematic in question grouped all bypass caps (one or two per IC, 4 − 5 total ICs) in a single +V->capacitors->GND block on the schematic.  The PCB, however, showed the caps very close to the appropriate component.  I have to agree with Olin and think that including the bypass caps in the schematic section relevant to the component would be easier to read.  However, there is a point of diminishing returns, as Alex and Herbert point out (given large BGA designs).

Based on my reading of the discussion, the vias I asked about were precautionary at best and don't hurt anything at worst.

I'll now return to lurking and researching my [this?] BS...

Thanks all,
Nate


'[EE] Parallel passives and sprinkled vias?'
2010\09\02@010530 by Gary Crowell
picon face
On Mon, Aug 30, 2010 at 5:58 AM, Olin Lathrop <spamBeGoneolin_piclistspamBeGonespamembedinc.com>wrote:

>
> ...  I try to run a separate ground
> and power net for something like a PIC with 1uF bypass caps between these
> two nets.  These local power and ground nets have a single connection to
> the
> rest of the boards's power and ground, with a 10uF cap accross the
> connection point.


If I understand your description correctly, doesn't this mean that the
return signal paths of all the PIC signals are confined to that single
pwr/gnd connection point?



----------------------------------------------
Gary A. Crowell Sr., P.E., CID+
Linkedin <http://www.linkedin.com/in/garyacrowellsr>
Elance<http://www.linkedin.com/redirect?url=http%3A%2F%2Fgaryacrowellsr%2Eelance%2Ecom&urlhash=kJm9

2010\09\02@073012 by Olin Lathrop

face picon face
Gary Crowell wrote:
> If I understand your description correctly, doesn't this mean that the
> return signal paths of all the PIC signals are confined to that single
> pwr/gnd connection point?

Yes, for those signals that go external to the local area of the PIC.  The
crystal lines do not, for example.

This means that the high frequency loop currents caused output signals being
driven by the PIC do go accross the wide ground plane.  However, note that
they would in a single ground plane scheme too.  The high frequency current
source in the PIC between the power and ground leads is generally much
bigger, and its current will be contained locally and not "contaminate" the
global ground plane.

This kind of board design is all about visualizing the high frequency
current loops, where they are, and what effect they will have.  We are used
to thinking about power current flowing into the Vdd pin and out the Vss pin
of a PIC.  This is true for the DC component, but if you only look at the
high frequency components the PIC actually becomes a current source, as do
other digital ICs.  Letting this current run accross the global ground plane
for a bit it just another way of describing a center fed patch antenna.

2010\09\02@110129 by RussellMc

face picon face
A point to be aware of is that there are several conflicting requirements
- this is engineering after all :-).

As Olin notes, you can "island" the processor and feed power current to and
from it via a single "highway". But, if you drive output loads that do not
have their ground return paths returned to the island, then you get loop
currents flowing elsewhere. This is understood and accepted. But in the
process you can create common paths with analog signals also leaving the
island  and returning 'by another route". It can be useful for lower current
analog signals to have their go and return paths fed back to the "island" -
either directly with dedicated go and return conductors, or as Olin notes,
by  trying to arrange for most signal current to flow by "directish" routes
back to whence it has come, and at the same time trying to make sure that
power currents do not flow over the same route. In extreme cases you can use
"guard rings" to create a constant potential around your signal leads, but
this is usually beyond what's needed in most cases.

In 'good old analog days' (cardboard box, lake, uphill both ways, snow ...)
where wiring was often  "point to point", it was common practice to (try to)
have a single ground point and to have ALL ground wiring return to this one
point and to not use chassis, bus bars etc as ground returns. This was
intended to minimise common impedance paths shared by various currents. If
two signals share a common conductor that has non zero impedance and if one
signal varies the voltage drop across this common impedance then the common
voltage  will be imposed on the second  signal. If the source is high
amplitude and the affected signal is low amplitude then the effect can be
very substantial.

Also, if grounds are interconnected at various points you can end up with
one or more "loops"  with non zero area that are not only transmitting
aerials  but also receiving aerials. The digital circuitry MAY not care but
the analog circuitry usually will. This is the classic "ground loop" which
causes hum in audio systems.

The common point ground and the distributed ground plane are in some ways
opposite ends of the continuum (connect anywhere versus connect at one
point) but are also aiming at the same thing - a perfect ground plane is a
"distributed single common point". The problems mentioned occur when this
"distributed common point" becomes non ideal or less ideal -  such as when
the signals on it become large enough to produce voltage differences, and
the points Olin raised are intended to attempt to push things back towards
"ideallity".  Murphy loves helping out when you try to achieve this :-).


             Russell McMahon






On 2 September 2010 23:30, Olin Lathrop <TakeThisOuTolin_piclistEraseMEspamspam_OUTembedinc.com> wrote:

{Quote hidden}

>

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