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'[EE] PHY interfaces - MII vs RMII'
2007\10\03@113208 by alan smith

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So I am looking at connecting a PHY to a DSP, and both parts support both MII and RMII.  From what I can gather, RMII is the newer standard, so besides being less pins used, is there a issue using RMII over MII ?  R does stand for reduced...but think thats just the pins.  My networking expert is on vacation..thus i turn to the list.

     
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2007\10\03@235746 by Vasile Surducan

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After a deep search for choosing the best eternet gigabit transciever
for one application and found that almost all PHY IC's have both the
RGMII and GMII standards. However at least on the FPGA side, GMII is
most frequent used. There is a small RX&TX bus difference, one is 8
bit, the other is 4 bit wide. Also there are different clocks for
different speed (on GMII is 2.5MHz for 10Mbps, 25MHz for 100Mbps and
125MHz for 1Gbps).

Vasile

On 10/3/07, alan smith <spam_OUTmicro_eng2TakeThisOuTspamyahoo.com> wrote:
> So I am looking at connecting a PHY to a DSP, and both parts support both MII and RMII.  From what I can gather, RMII is the newer standard, so besides being less pins used, is there a issue using RMII over MII ?  R does stand for reduced...but think thats just the pins.  My networking expert is on vacation..thus i turn to the list.
>
>
> ---------------------------------
> Don't let your dream ride pass you by.    Make it a reality with Yahoo! Autos.
> -

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