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'[EE] PCB Via size'
2007\01\18@120637 by

I have a design that is controlling an incandescent lamp with a
current of about 1 Amp.  I am not as concerned with the voltage drop as
I am with overall reliability and ensuring that the via does not become
a fuse.  There are many places that help in calculating the suggested
PCB trace width for a given current but what about the via?

The calculators tell me that the trace should be 30 mils wide.  (I use
40 to be safe.)  Now when I need to go from top to bottom metal, what
size via (also called feed-thru holes) is required?  Drill size and
overall diameter of the 'cover' metal?  The only reference that I was
able to find indicated that the via drill size should be greater than
the metal width/3.  So for a 40mil wide metal the drill size should be
greater than 14mils.

Thanks for any suggestions.
Phil

--
--------------------------------
Long ago when men cursed and beat the
ground with sticks,  it was called witchcraft..

Today, it's called golf.

> -----Original Message-----
> From: piclist-bouncesmit.edu [piclist-bouncesmit.edu]On Behalf
> Of Phil Keller
> Sent: 18 January 2007 17:04
> To: PICLIST Post
> Subject: [EE] PCB Via size
>
>
>   I have a design that is controlling an incandescent lamp with a
> current of about 1 Amp.  I am not as concerned with the voltage drop as
> I am with overall reliability and ensuring that the via does not become
> a fuse.  There are many places that help in calculating the suggested
> PCB trace width for a given current but what about the via?
>
>   The calculators tell me that the trace should be 30 mils wide.  (I use
> 40 to be safe.)  Now when I need to go from top to bottom metal, what
> size via (also called feed-thru holes) is required?
i'd imagine the first thing you'd want to find out is the thickness of the plating (which is likely to be substantially thinner than the top/bottom copper) from there you can calculate the holesize required to give your via equivilent CSA to your track.

multiple vias are probablly a good idea as hole area goes with the square of hole diameter while plating CSA only goes linearly with hole diameter.

another option if you are pushed for space is to put a peice of suitablly rated wire through the via and solder it on both sides.

One solution is to calculate the copper area of your "standard" via and
compare this to the recommended trace area.  Then use multiple vias
instead of just one.  If one via calcs out to being close, then use ten
vias and sleep at night.

Something else to do is make some measurements of voltage drop across
vias that were made by the board shop you expect to use (if possible).

Take a bare board, locate an accessible trace with a via and apply a
current limited supply to it, preferably at say 1 amp.  Then take a
voltmeter and measure the drop along the trace.   This will give you at
least a ballpark idea of what the resistance is across the via and thus
what the I2R losses might be approximately.

Phil Keller wrote:
{Quote hidden}

piclist-bounces@mit.edu wrote:
>   The calculators tell me that the trace should be 30 mils
> wide.  (I use 40 to be safe.)

Bear in mind the underlying assumptions of the calculator you are using.
Some examples of assumptions are temperature rise, copper thickness,
external layer, etc. Generally the assumptions err towards the
conservative side.

> Now when I need to go from top
> to bottom metal, what size via (also called feed-thru holes)
> is required?

Good question, and one that I am sure many other people have wondered
about. My first attempt would be to equate the cross-sectional area of
your trace to the cross-sectional area of the via. Your board
manufacturer should be able to tell you plating thickness. As far as I
know, vias will generally have thinner copper than traces. this plus
your drill size should be enough to determine the cross-sectional area.

My second reaction is that since you're talking about a lightbulb at one
ampere, its unlikely you will have problems. Make the via as large as
you can for your existing 40-mil trace and be done with it.

> The only reference that I was able to find indicated that
> the via drill size should be greater than the metal width/3.
> So for a 40mil wide metal the drill size should be greater
> than 14mils.

got a reference? I'd be interested in this.

The reference I was using for via size is:
http://www.ultracad.com/articles/viacurrents.pdf

The fab house I use has a trace thickness of 1.3mil-2mil  (standard
1oz/sqft) and  a via wall thickness of 0.8mil-1.2mil.

Phil

--
--------------------------------
Long ago when men cursed and beat the
ground with sticks,  it was called witchcraft..

Today, it's called golf.

> Take a bare board, locate an accessible trace with a via and apply a
> current limited supply to it, preferably at say 1 amp.  Then take a
> voltmeter and measure the drop along the trace.   This will give you at
> least a ballpark idea of what the resistance is across the via and thus
> what the I2R losses might be approximately.
also if you have a board that is scrap anyway you could use it for some destructive via testing, take your standard via and crank up the current through it until you vaporise something.

Two small vias a better than a large one, three are much better than two...
http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/

Vasile

On 1/18/07, Phil Keller <Philpkeller.net> wrote:
{Quote hidden}

> -
piclist-bounces@mit.edu wrote:
>   The reference I was using for via size is:
> http://www.ultracad.com/articles/viacurrents.pdf

I noticed they made the assumption that via wall thickness was equal to
trace thickness, and called it T. Then they assumed T is small wrt to
width and ignored it in the final equation, and rounded PI tp 3. Ok, ill
buy that .040 >> 0.0008, but I'd want to do the calculations myself
before using the Dia = width/3 rule. I'm not sure about their formula
for cross-sectional area of the via, either. Maybe they did some
simplifying, but I'd take a second look at that.

>   The fab house I use has a trace thickness of 1.3mil-2mil  (standard
> 1oz/sqft) and  a via wall thickness of 0.8mil-1.2mil.

always assume the worst case, so use 1.3 for the thickness of the trace
and 0.8 for the via thickness. Think of the via as two circles, the area
of one subtracted from the other to get the cross-sectional area of the
barrel. Set the two areas equal and solve for drill size as they did in
the article.

comments anyone?

> -----Original Message-----
> From: piclist-bouncesmit.edu On Behalf Of peisermaridgid.com
> Sent: Thursday, January 18, 2007 1:13 PM
>
<snip>
>
> > The only reference that I was able to find indicated that
> > the via drill size should be greater than the metal width/3.
> > So for a 40mil wide metal the drill size should be greater
> > than 14mils.
>
> got a reference? I'd be interested in this.

I don't have a web reference but look at it this way. If you roll up a 40
mil trace to be like a via you will have a cylinder. The trace width equals
the circumference so you calculate the diameter from the circumference
(diameter = circumference / pi). I suspect the original source just used the
handy single digit approximation of pi.

Paul

piclist-bounces@mit.edu wrote:
> Two small vias a better than a large one, three are much better than
> two...
> http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/

thanks for that link. There is a TI document cited as a reference. I
obviously have not had more than a few minutes to glance at it, but to
steal Russell's catchphrase, it looks "utterly superb"

> -----Original Message-----
> From: piclist-bouncesmit.edu On Behalf Of Phil Keller
> Sent: Thursday, January 18, 2007 1:42 PM
>
>   The reference I was using for via size is:
> www.ultracad.com/articles/viacurrents.pdf
>
>   The fab house I use has a trace thickness of 1.3mil-2mil  (standard
> 1oz/sqft) and  a via wall thickness of 0.8mil-1.2mil.
>
> Phil

Since the via plating can be almost 1/2 the minimum trace thickness, I'd use
a factor of 2 for safety. So with 40mil selected for regular traces your
total calculation is (40mil/pi)*2 =~ 25.5. Then of course increase it for
extra safety.

Paul

peiserma@ridgid.com wrote:
> piclist-bouncesmit.edu wrote:
>> Two small vias a better than a large one, three are much better than
>> two...
>> http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/
>
>
> thanks for that link. There is a TI document cited as a reference. I
> obviously have not had more than a few minutes to glance at it, but to
> steal Russell's catchphrase, it looks "utterly superb"
>

There is one item at that site that pertains to a discussion on printing
your own pcbs (from yesterdays piclist?):

http://circuitcalculator.com/wordpress/2006/06/14/conductive-ink-traces/

It is based on using Dow Corning PI-2000 series of Silver Polymeric
Interconnect Materials.

piclist-bounces@mit.edu wrote:
>> -----Original Message-----
>> From: piclist-bouncesmit.edu On Behalf Of Phil Keller
>> Sent: Thursday, January 18, 2007 1:42 PM
>>
>>   The reference I was using for via size is:
>> www.ultracad.com/articles/viacurrents.pdf
>>
>>   The fab house I use has a trace thickness of 1.3mil-2mil (standard
>> 1oz/sqft) and  a via wall thickness of 0.8mil-1.2mil.
>>
>> Phil
>
> Since the via plating can be almost 1/2 the minimum trace
> thickness, I'd use a factor of 2 for safety. So with 40mil
> selected for regular traces your total calculation is
> (40mil/pi)*2 =~ 25.5. Then of course increase it for extra safety.

I just couldn't resist getting out the pen and paper. If maintaining the
same cross-sectional area is the only concern, then you need a via with
OD 21.5 mil and ID 19.9 mil to give you the same cross-sectional area as
a 40 mil by 1.3 mil trace.  I like your approximating much better than
the ultracad pdf.

Note how the via is specified becomes important. Do you give the mfg. an
inner diameter and let them pick the drill, or do you give them actual
drill sizes?

Note the TI document in the link Vasile posted does say plated copper
has a higher resistivity.  I don't think an incandescent at 1A is a
critical application, so I wouldn't worry about the via too much in this
particular case.

Yes I did notice the 'simplifying' assumption.  Taking the fact that
the via is 1/2 as thick as trace metal this means that the via should be
greater than 2/3 of the metal width.  Also from the same article (I
believe.  I have read so many and they are beginning to blur.)  and the
suggestion that many is better than one,  the SUM of the via diameters
should be greater than 2/3 of the metal width.

So in this case a 40mil trace could have
- one 27mil via,
- two 14mil vias,
- three 10 mil vias

Thanks to all for the suggestions and the discussion.  I now have a
new "rule-of-thumb" to use.

Phil

--
--------------------------------
Long ago when men cursed and beat the
ground with sticks,  it was called witchcraft..

Today, it's called golf.

> -----Original Message-----
> From: piclist-bouncesmit.edu On Behalf Of peisermaridgid.com
> Sent: Thursday, January 18, 2007 5:04 PM
<snip>
>
> Note how the via is specified becomes important. Do you give the mfg.
> an inner diameter and let them pick the drill, or do you give them
> actual drill sizes?

The many PCB manufacturers I've used over the past 25 years vary greatly in
plating thickness. So I always provide the finished hole size and let the
PCB guys figure out what size hole to drill before plating. This has the
added benefit of not having to change the design files every time the
plating process gets improved or the vendor is changed. I put a note on the
drill drawing that states the sizes are "finished hole sizes (after
plating)". If I was designing a PCB where current carrying capacity was
important, I would also add a note to the drill drawing on minimum plating
thickness requirements and then also put a note in the readme file.

Paul

Remember...when you drop in mulitple via's, if you just put them in a straight line, the first is going to take the bulk of the current, the others whatever can be delivered.  So, try to place them so you get an even flow into them, and it will also lower the inductive properties

Phil Keller <Philpkeller.net> wrote:  Yes I did notice the 'simplifying' assumption. Taking the fact that
the via is 1/2 as thick as trace metal this means that the via should be
greater than 2/3 of the metal width. Also from the same article (I
believe. I have read so many and they are beginning to blur.) and the
suggestion that many is better than one, the SUM of the via diameters
should be greater than 2/3 of the metal width.

So in this case a 40mil trace could have
- one 27mil via,
- two 14mil vias,
- three 10 mil vias

Thanks to all for the suggestions and the discussion. I now have a
new "rule-of-thumb" to use.

Phil

--
--------------------------------
Long ago when men cursed and beat the
ground with sticks, it was called witchcraft..

Today, it's called golf.

>
>
> The many PCB manufacturers I've used over the past 25 years vary greatly
> in
> plating thickness. So I always provide the finished hole size and let the
> PCB guys figure out what size hole to drill before plating. This has the
> added benefit of not having to change the design files every time the
> plating process gets improved or the vendor is changed. I put a note on
> the
> drill drawing that states the sizes are "finished hole sizes (after
> plating)". If I was designing a PCB where current carrying capacity was
> important, I would also add a note to the drill drawing on minimum plating
> thickness requirements and then also put a note in the readme file.

That's really the only way to fly.. Let them worry about their process
variables, just specify the end result, and verify that they did achieve it.

I also put notes with the job files that the gerbers are not to be altered
by them other than in panelization.
I've seen too many instances of them plopping a cute little logo into
"unused space" that was important to remain unused, like in stripline/RF
designs, or high voltage sections.
On 1/22/07, David VanHorn <dvanhornmicrobrix.com> wrote:
{Quote hidden}

There are deepest manufacturing problems David.
At really large density (small via rings) they must add tear drops (if
there are not already there), and struggle with laser/mechanical
drilled holes like 5-6mil (0.125-0.15mm) and routes/clearances below 4
mil (0.10mm) where any acid trap becomes a mess.
Only a few houses are able to do this even they claim it's
manufacturable and they handle the technology. The best way is to do
yourself the panelisation for such restrictive designs. Unfortunately
sometimes the PCB houses does not gave you enough informations to
adjust your design acordingly with their technology.

greetings,
Vasile
>I've seen too many instances of them plopping a cute little logo
>into "unused space" that was important to remain unused, like in
>stripline/RF designs, or high voltage sections.

You mean you didn't mark out an area for the manufacturers "traceability
mark" ?? If they put anything outside such an area I would go ballistic, but
give them their own sandbox and they are happy.

alan smith wrote:

> Remember...when you drop in mulitple via's, if you just put them in a
> straight line, the first is going to take the bulk of the current, the
> others whatever can be delivered.

How do you calculate how much current each via carries? Aren't they just
resistors (I'm talking about DC here, disregarding inductive effects)?

Considering such a configuration (trace on top, trace on bottom, 4 vias in
a straight line):

+----+----+----+----...
|    |    |    |
...----+----+----+----+

Why would any of the vias get more current than any other? If it is in fact
the first, which one is the first -- the left or the right?

Gerhard

>
>
> There are deepest manufacturing problems David.
> At really large density (small via rings) they must add tear drops (if
> there are not already there), and struggle with laser/mechanical
> drilled holes like 5-6mil (0.125-0.15mm) and routes/clearances below 4
> mil (0.10mm) where any acid trap becomes a mess.
> Only a few houses are able to do this even they claim it's
> manufacturable and they handle the technology. The best way is to do
> yourself the panelisation for such restrictive designs. Unfortunately
> sometimes the PCB houses does not gave you enough informations to
> adjust your design acordingly with their technology.

Yeah, I know.. :(

But if they mod my files, then I never get to know what needs to be changed,
and I don't even necessarily get to know what they are changing.
>
> You mean you didn't mark out an area for the manufacturers "traceability
> mark" ?? If they put anything outside such an area I would go ballistic,
> but
> give them their own sandbox and they are happy.

On the last several boards I've done, there just wasn't any room at all.  We
were fighting for single mils.
At my last job, had a very nice excel file that calculated this all out....im sure I have it someplace but can't lay my hands on it right now.  But it was on the web...it it conformed to the standards.

Now, if you guys haven't looked at http://www.pcbstandards.com, take a gander.  Its full of good stuff, including a bunch of calculators, etc.  Also forums for different design packages...but not Eagle.

Gerhard Fiedler <listsconnectionbrazil.com> wrote:
alan smith wrote:

> Remember...when you drop in mulitple via's, if you just put them in a
> straight line, the first is going to take the bulk of the current, the
> others whatever can be delivered.

How do you calculate how much current each via carries? Aren't they just
resistors (I'm talking about DC here, disregarding inductive effects)?

Considering such a configuration (trace on top, trace on bottom, 4 vias in
a straight line):

+----+----+----+----...
| | | |
...----+----+----+----+

Why would any of the vias get more current than any other? If it is in fact
the first, which one is the first -- the left or the right?

Gerhard

I just installed Ubuntu on one of my machines, and I see that they have a
layout package with autorouter.
I haven't tried it yet, but it's interesting.

On Jan 22, 2007, at 9:35 AM, alan smith wrote:

> when you drop in mulitple via's, if you just put them in a
> straight line, the first is going to take the bulk of the current

Um, I don't think so.  At worst you have a resistor network with
some very small resistances, and you'll get SLIGHTLY uneven current
through the vias; intuitive or not...

BillW

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