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'[EE] PAL, CPLD, FPGA'
2011\03\05@023723 by V G

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Just out of curiosity.

I've been reading the wikipedia pages, as well as some other websites on the
topic of PAL/CPLD/FPGA, but I still don't understand the following:

1. What are they?
2. How do they work?
3. Why are they used?
4. How are they used?
5. I've seen the term "parallel processing" mentioned a lot. How does this
tie in with PAL/CPLD/FPGA?
6. What is the difference between PAL, CPLD, and FPGA and under what
circumstances would you use each of them in?
7. Why not use a microcontroller such a PIC to do the work?
8. How does each one of them compare to a microcontroller, let's say PIC32,
in terms of cost, processing power, complexity, etc?
9. Are simple development boards for them expensive? I'm interested in
messing around with them. How is programming done?

I know those are a lot of questions, and *someone* is going to tell me to
google it, but I assure you all that I have, and would prefer answers from
human beings in this case.

Humans give insight.

Google does not

2011\03\05@043156 by Oli Glaser

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On 05/03/2011 07:36, V G wrote:
> Just out of curiosity.
>
> I've been reading the wikipedia pages, as well as some other websites on the
> topic of PAL/CPLD/FPGA, but I still don't understand the following:

I'll give a few of these a go... :-)

> 1. What are they?

Very roughly, they are just a load of logic gates with programmable switches in between. This means you can set them up to perform all sorts of different functions (by "wiring" the gates together as you like)
 Kind of like designing your own chip.

> 2. How do they work?

After programming, like any other digital chip, except they can be changed.

> 3. Why are they used?

They are very versatile and fast. For example a design I am prototyping reads ADCs at >400Msps (400MBps) which an FPGA is used for (try doing that with a PIC)
Sometimes maybe you just need a small PLD for "glue" logic (see recent post on CPLD) or similar (and there is no standard logic solution available)
I believe they are also used during the development of ASICs to speed up design/testing/debugging (much cheaper than actually making the chips then finding a problem)


> 4. How are they used?
> 5. I've seen the term "parallel processing" mentioned a lot. How does this
> tie in with PAL/CPLD/FPGA?

It's easy to do many things in parallel, since you are in control of how wide the bus is and the logic. Say you had a very complex mathematical operation that needs to happen very quickly - you can optimise (the whole chip if necessary) completely *just* for that operation, as opposed to a general purpose uC which needs to be able to do lots of other things too (a uC that could only perform 1 instruction would be pretty useless)

> 6. What is the difference between PAL, CPLD, and FPGA and under what
> circumstances would you use each of them in?
> 7. Why not use a microcontroller such a PIC to do the work?
> 8. How does each one of them compare to a microcontroller, let's say PIC32,
> in terms of cost, processing power, complexity, etc?
> 9. Are simple development boards for them expensive? I'm interested in
> messing around with them. How is programming done?

There are cheap dev boards and programmers floating around (eBay etc - copies of the Xilinx, Altera for a lot less) but getting up to speed is harder than with uCs (less online info/forums etc) I think due to them having far less hobbyist/small company use.
I actually designed my own dev board to start with, as I thought it would be a good way to learn about how everything worked - which it was (a lot more involved though)

> I know those are a lot of questions, and *someone* is going to tell me to
> google it, but I assure you all that I have, and would prefer answers from
> human beings in this case.
>
> Humans give insight.
>
> Google does not.

Guggle is not great for FPGAs - I would grab a few books on the subject, couple I can remember reading - "A design warriors guide to FPGAs" (I think that's right) "FPGA proptoyping with Verilog examples" (uses a cheapish Xilinx board if you can get hold of it still - eBay..) "Verilog - a guide to digital design and synthesis"

See what other books are out there, should be some decent (new) ones available.



2011\03\05@051651 by V G

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On Sat, Mar 5, 2011 at 4:31 AM, Oli Glaser <spam_OUToli.glaserTakeThisOuTspamtalktalk.net> wrote:

{Quote hidden}

Thanks for the detailed reply, Oli.

1. To start off with basic things (hobby use, but with potential to do crazy
things like reading at 400M samples/s), which would you recommend,  PAL,
CPLD, or FPGA?

2. How is "speed" actually rated for these types of devices? Clock speed? If
so, what is the clock speed generally around? Without even thinking, I would
assume reading at 400M samples/s would require at least 400 MHz. Do these
things use crystals as a clock source

2011\03\05@052646 by V G

picon face
Relevant:

This is a really cool site I found: http://www.fpga4fun.com

2011\03\05@053017 by William \Chops\ Westfield

face picon face

On Mar 5, 2011, at 2:16 AM, V G wrote:

> 1. To start off with basic things (hobby use, but with potential to  
> do crazy
> things like reading at 400M samples/s), which would you recommend,  
> PAL,
> CPLD, or FPGA?

An FPGA is the most general implementation (largest variety of things  that can be interconnected in the most ways.)  CPLDs are cheaper and  more limited.  PALs are best thought of as direct replacements for  relatively small numbers of logic chips.  A PAL could implement  something like an address decoder, a CPLD an IO chip, and an FPGA can  implement a microcontroller.

Check out:  http://dangerousprototypes.com/category/fpga/

BillW

2011\03\05@054412 by Oli Glaser

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On 05/03/2011 10:16, V G wrote:
> 1. To start off with basic things (hobby use, but with potential to do crazy
> things like reading at 400M samples/s), which would you recommend,  PAL,
> CPLD, or FPGA?

PAL is a general term for CPLDs, FPGAs etc..
To start off with the basic stuff, I would go for a small FPGA or CPLD. However you can do a simple design on any of them as it's up to you how many gates you use - for instance you could use a 1M gate FPGA and just implement a simple counter/adder or something (it would be a very expensive counter though :-)  )
I started with FPGAs as you can probably do the most with them, though CPLDs have their uses/advantages too.


> 2. How is "speed" actually rated for these types of devices? Clock speed? If
> so, what is the clock speed generally around? Without even thinking, I would
> assume reading at 400M samples/s would require at least 400 MHz. Do these
> things use crystals as a clock source?

Speed is difficult as it depends what you do with them - the ratings are roughly for the fastest switching the gates are capable of, though this will drop quickly as complexity increases. For example you might have a 350MHz FPGA - an 8 bit counter might run at 300MHz on there, but a processor core (8051 etc) might only run at 50MHz. Often the datasheets will give rough guides of what speeds various things will run at.
The clock will usually be driven by a lower speed crystal oscillator into a PLL/DLL on the FPGA to generate the high speed clock. Or if you want you can drive the FPGA directly from the crystal at a lower speed.

2011\03\05@054744 by Oli Glaser

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On 05/03/2011 10:43, Oli Glaser wrote:
> PAL is a general term for CPLDs, FPGAs etc..
Then above is not right - to correct myself - I meant/read PLD.
PALs are smaller devices.

2011\03\05@055341 by Oli Glaser

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On 05/03/2011 10:26, V G wrote:
> Relevant:
>
> This is a really cool site I found: http://www.fpga4fun.com/

Yep - they sell a few nice little (well documented) dev boards too IIRC. A good place to start (one of the very few)
EDA board is good forum wise also.

2011\03\05@060320 by Michael Watterson

face picon face

I'm very inexpert at FPGA and not yet completed any serious project...


On 05/03/2011 07:36, V G wrote:
> I've been reading the wikipedia pages, as well as some other websites on the
> topic of PAL/CPLD/FPGA, but I still don't understand the following:
>
> 1. What are they?
Programmable Logic. Instead of separate standard logic parts (much more space and expense) or a Program on a Microcontroller (much much slower).
> 2. How do they work?
Invented by some guys fed up designing Z80 (and probably especially Z8000 which was a disaster). Originally The idea of having groups of standard NAND gates, NOR gates and X / Y wiring matrix of fuses to "blow" to create your logic function,

Modern gates have reprogrammable interconnections.
Complexity
PAL -> CPLD -> FPGA
At lower end they really are gates. At high end (all FPGAs) the logic is implemented by RAM look up table and often the configuration must be loaded at boot time from External FLash. some have Flash built in. Also on better parts are Bus drivers, Hardware multiply & Add (basic for CPUs and DSPs and wasteful to do from scratch).
> 3. Why are they used?
To shrink several large circuit boards to one chip (save money & space)
Avoid ASIC in a prototype or "proof of concept" or if production is  less than 500k
Allow changes in field via JTAG or companion CPU
> 4. How are they used?
You use CAE tools and can design via logic table, HDL, verilog, DSP coeffients or schematic in any combination.

> 5. I've seen the term "parallel processing" mentioned a lot. How does this
> tie in with PAL/CPLD/FPGA?
The design can use any mix of parallel, pipelined and serial configuration up to limit of "gates".
if you have 16 hardware Multipliers and the design needs 128 multiplies, the CAE can pipeline the 16 serialised (multiplexed) as 128 (a CPU can do many millions of multiplies in a function call with one Multiplier). Or the data can have 8 to 32 parallel paths instead of one pipeline. If the real number Multipliers is less than design needs, your clock rate is slower, thus 128 parallel data paths with only 16 multipliers means only 16 multiplications at once, So it multiplex had no overhead the max clock rate would be 8 times slower.

> 6. What is the difference between PAL, CPLD, and FPGA and under what
> circumstances would you use each of them in?
Complexity, speed, cost see above.
A simple PAL can maybe replace a handful of 74 series chips. The highest end FPGA can implement ethernet, USB, IDE, VGA port all with very little external hardware and implement an entire PC motherboard in one FPGA, with multiple "soft" RISC CPU (likely no FPU) "cores". Many CPU are available as libraries. 6502, Z80 etc can be faster than original. MIPs, ARM faster or slower.
Latest Xilinx FPGA has 2 x ARM hardware cores and FPGA on one chip.
Low end parts do MHz clock. Highest end parts maybe 20Gbps per pin trhoughput.

> 7. Why not use a microcontroller such a PIC to do the work?
yes. if an overall speed of 10kHz (some DSP) to 1MHz total average throughput is OK. 12MIPs on 18F. And 4 to 50 pins
any PAL / CPLD / FPGA can beat that. A $15 Spartan FPGA may manage several MHz data rate with more DSP than the 18F can manage at 10kHz. Or do simpler stuff up to 400MHz. Also with 100s of pins of I/O simultaneously..
many Programmable Logic have extremely high and usable I/O, so those are BGA (Ball Grid Array)

Some things are easier to write a program for, other things are more easy and reliably designed in Logic.
The "programming" lanaguages (two main ones) are not sequential functional languages that generate a program that is executed. They are mostly parallel descriptions of the configuration. Write "regular" style stuff and see 3 lines eat the entire chip!

> 8. How does each one of them compare to a microcontroller, let's say PIC32,
> in terms of cost, processing power, complexity, etc?
FPGA "faster" than PC32 with more I/O could be $5. A high end FPGA to prototype GHz speed ASIC part with CPU core and much DSP many $k

> 9. Are simple development boards for them expensive? I'm interested in
> messing around with them. How is programming done?
>
No.
http://www.techtir.ie/node/1003026
Well supported with Tutorials and plenty of features
www.trenz-electronic.de/products/fpga-boards/trenz-electronic/te0300-spartan-3e-series.html
very low on FPGA performance scale. Actual chip is very cheap.

List
http://www.techtir.ie/node/1001701

2011\03\05@072431 by Oli Glaser

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On 05/03/2011 10:43, Oli Glaser wrote:
> Speed is difficult as it depends what you do with them - the ratings are
> roughly for the fastest switching the gates are capable of, though this
> will drop quickly as complexity increases.

Just to clarify here - I didn't mean that the actual gate switching speeds will drop as the complexity increases, rather that the timing constraints become tighter when the design becomes more complex and path delays increase (so you have to drop the clock speed)

2011\03\05@113845 by Gerhard Fiedler

picon face
Oli Glaser wrote:

> On 05/03/2011 10:16, V G wrote:
>> 2. How is "speed" actually rated for these types of devices? Clock
>> speed? If so, what is the clock speed generally around? Without even
>> thinking, I would assume reading at 400M samples/s would require at
>> least 400 MHz. Do these things use crystals as a clock source?
>
> Speed is difficult as it depends what you do with them - the ratings
> are roughly for the fastest switching the gates are capable of,
> though this will drop quickly as complexity increases. For example
> you might have a 350MHz FPGA - an 8 bit counter might run at 300MHz
> on there, but a processor core (8051 etc) might only run at 50MHz.
> Often the datasheets will give rough guides of what speeds various
> things will run at. The clock will usually be driven by a lower speed
> crystal oscillator into a PLL/DLL on the FPGA to generate the high
> speed clock. Or if you want you can drive the FPGA directly from the
> crystal at a lower speed.

In certain applications, you don't even use a clock like in a
synchronous device like a microcontroller. While they all have some sort
of clock line that feeds the cells, they can work independently of the
system clock -- just like any other logic. This is especially common
when using e.g. CPLDs as glue logic.
The speed is basically limited by the maximum clock speed (for
clock-based designs) and the propagation delays. Which, as Oli says,
depends on the complexity of a given design, because the more gates and
flip-flops you put in series in a signal path, the slower it becomes, as
the delays add up for each element.

Basically, while you program these, it's more like hardware design than
writing a program for a micro. If you look at a manual for one of these,
you'll see how the internal structure is and everything that has been
said will become clearer.

Gerhar

2011\03\05@115747 by Herbert Graf

picon face
On Sat, 2011-03-05 at 02:36 -0500, V G wrote:
> Just out of curiosity.
>
> I've been reading the wikipedia pages, as well as some other websites on the
> topic of PAL/CPLD/FPGA, but I still don't understand the following:
>
> 1. What are they?

Think of them as user configurable digital asics.

> 2. How do they work?

Depends on which one. Google has lots of references.

> 3. Why are they used?

Because they fulfill the requirements of a particular design (as with
any other part).

> 4. How are they used?

Really there are 2 main uses for programmable logic:

1) Prototyping digital designs - being user reconfigurable you can put
your prototype HDL design into these parts and debug any problems. It's
a step above simulation, and allows you to catch problems that sims are
not that great at catching.

2) Implementing designs where going to an ASIC isn't financially viable.
This means either R&D type products, where the company only needs say
100 parts, or commercial products that are "niche" enough not to justify
putting it in an ASIC (another case is if the turnaround time of
spinning the ASIC is too long/costly). Examples of this are broadcast
video. Alot of their widgets use FPGAs, since they don't need that many
of them, and the profit margins are so high as to warrant use of an
FPGA.

> 5. I've seen the term "parallel processing" mentioned a lot. How does this
> tie in with PAL/CPLD/FPGA?

Well, it's digital logic, digital logic tends to be very parallel (since
if your work task doesn't require the parallel benefits you'd just use a
CPU/MCU and software to solve the problem).

> 6. What is the difference between PAL, CPLD, and FPGA and under what
> circumstances would you use each of them in?

PALs are mostly dead, I wouldn't bother looking into them.

CPLDs CAN be thought of as "small" FPGAs, so if your design fits in a
CPLD you'd probably go with that. Otherwise go with an FPGA.

That said, FPGAs have REALLY encroached the CPLD space, so much so that
most designers just skip over CPLDs these days (you can buy a tiny FPGA
for just a buck or 2 in quantity).

> 7. Why not use a microcontroller such a PIC to do the work?

Because the task at hand wouldn't either be possible or would be 2 slow
in a CPU/MCU. For example, implementing a MP3 decoder that operates in
real time can be very easily and cheaply implemented on a very small
FPGA, doing the same in a CPU/MCU would require alot more horsepower.

Decryption is another area where the inherently parallel nature of FPGAs
trumps CPU/MCUs.

> 8. How does each one of them compare to a microcontroller, let's say PIC32,
> in terms of cost, processing power, complexity, etc?

Apples and oranges. That's like comparing op-amps and SRAM.

> 9. Are simple development boards for them expensive? I'm interested in
> messing around with them. How is programming done?

No, there's lots out there that are less then $100. Google search turns
up several.

TTYL

2011\03\05@120228 by Herbert Graf

picon face
On Sat, 2011-03-05 at 05:16 -0500, V G wrote:
> Thanks for the detailed reply, Oli.
>
> 1. To start off with basic things (hobby use, but with potential to do crazy
> things like reading at 400M samples/s), which would you recommend,  PAL,
> CPLD, or FPGA?

Start with FPGAs.

> 2. How is "speed" actually rated for these types of devices? Clock speed? If
> so, what is the clock speed generally around? Without even thinking, I would
> assume reading at 400M samples/s would require at least 400 MHz. Do these
> things use crystals as a clock source?

Clocking in an FPGA is a whole other story.

There is no "one" clock in an FPGA, you can define pretty much as many
clocks as you require (up to the clock network routing in the particular
FPGA you use).

As for source, that depends. Most FPGAs don't have crystal drivers, so
you need to supply either a canned oscillator or other clock source (say
a clock chip).

That said, FPGAs have INCREDIBLE internal clock generation capabilities.
Most have numerous PLLs and clock dividing logic. Many have clock delay
blocks as well. Feed an FPGA one clock and your design can use dozens if
need be.

One design I did had about 10 different clocks, ranging from ~300kHz, to
80MHz, to 148.5MHz.

TTYL

2011\03\05@120532 by Herbert Graf

picon face
On Sat, 2011-03-05 at 10:43 +0000, Oli Glaser wrote:
> On 05/03/2011 10:16, V G wrote:
> > 1. To start off with basic things (hobby use, but with potential to do crazy
> > things like reading at 400M samples/s), which would you recommend,  PAL,
> > CPLD, or FPGA?
>
> PAL is a general term for CPLDs, FPGAs etc..

To be nitpicky, no, PAL is a certain class of programmable logic
devices:

http://en.wikipedia.org/wiki/Programmable_Array_Logic

PLD is I think the generic term you're thinking of?

TTYL

2011\03\05@123224 by Isaac Marino Bavaresco

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Em 5/3/2011 13:57, Herbert Graf escreveu:
>> 4. How are they used?
> Really there are 2 main uses for programmable logic:
>
> 1) Prototyping digital designs - being user reconfigurable you can put
> your prototype HDL design into these parts and debug any problems. It's
> a step above simulation, and allows you to catch problems that sims are
> not that great at catching.
>
> 2) Implementing designs where going to an ASIC isn't financially viable.
> This means either R&D type products, where the company only needs say
> 100 parts, or commercial products that are "niche" enough not to justify
> putting it in an ASIC (another case is if the turnaround time of
> spinning the ASIC is too long/costly). Examples of this are broadcast
> video. Alot of their widgets use FPGAs, since they don't need that many
> of them, and the profit margins are so high as to warrant use of an
> FPGA.


Don't forget that they are reprogrammable, so they are upgradeable. Some
designs may need updates or functionality changes after deployment, and
some may need to be reconfigured regularly.

If you use an ASIC, you are stuck with the initial design.


{Quote hidden}

FPGAs and CPLDs serve the same functions, but they have different
architectures, "logical blocks" (FPGA) versus "macrocells" (CPLDs),
something like the difference between Von Neuman and Harward architectures.

FPGAs are usually much larger than CPLDs and some load their "program"
at power-up (boot-up) from an external memory. CPLDs are (re-)programmed
with a programmer.
So FPGAs fit much larger designs and may be updated by software.


Isaac

2011\03\05@142845 by Philip Pemberton

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On 05/03/11 17:02, Herbert Graf wrote:
> That said, FPGAs have INCREDIBLE internal clock generation capabilities.
> Most have numerous PLLs and clock dividing logic. Many have clock delay
> blocks as well. Feed an FPGA one clock and your design can use dozens if
> need be.

Although in synchronous designs (which is what FPGAs are really good for) it's frowned upon to use logic to generate a clock. That is, to have a clock driving (e.g.) a counter, then output a clock based on the value of that counter. The changing values can cause issues with glitches.

As a bonus you also get clock skew -- 1*Tpd for each gate the clock passes through. So if you do too much division of a single clock, you get setup and hold time violations. These nasty little critters can, will and often do make designs go metastable -- "it worked five minutes ago, but it doesn't work now". Or there's the even more insidious "It works on that board, but not this one..!"

The more generally accepted way to do it is to have a single master clock, and use division logic to generate clock enable signals. The clocked circuitry essentially ANDs the clock and CKE at the terminus. Your clock signal goes along one of the low-latency clock routes inside the FPGA, while the CKE goes through the logic fabric. This helps to reduce the risk of a sample/hold violation.

FPGA design is fun.

-- Phil.
.....piclistKILLspamspam@spam@philpem.me.uk
http://www.philpem.me.uk

2011\03\05@174700 by Oli Glaser

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On 05/03/2011 17:05, Herbert Graf wrote:
> On Sat, 2011-03-05 at 10:43 +0000, Oli Glaser wrote:
>> On 05/03/2011 10:16, V G wrote:
>>> 1. To start off with basic things (hobby use, but with potential to do crazy
>>> things like reading at 400M samples/s), which would you recommend,  PAL,
>>> CPLD, or FPGA?
>> PAL is a general term for CPLDs, FPGAs etc..
> To be nitpicky, no, PAL is a certain class of programmable logic
> devices:
>
> http://en.wikipedia.org/wiki/Programmable_Array_Logic
>
> PLD is I think the generic term you're thinking of?
>
> TTYL
>

Yes it was - check out my corrective post a couple of minutes afterwards...  ;-)
(in which there is also a mistake - first word is meant to be "The"...)

2011\03\05@175825 by V G

picon face
On Sat, Mar 5, 2011 at 11:57 AM, Herbert Graf <hkgrafspamKILLspamgmail.com> wrote:

>  > 7. Why not use a microcontroller such a PIC to do the work?
>
> Because the task at hand wouldn't either be possible or would be 2 slow
> in a CPU/MCU. For example, implementing a MP3 decoder that operates in
> real time can be very easily and cheaply implemented on a very small
> FPGA, doing the same in a CPU/MCU would require alot more horsepower.
>
> Decryption is another area where the inherently parallel nature of FPGAs
> trumps CPU/MCUs.
>

I thought MP3 decoding was very serial in nature

2011\03\05@183011 by Olin Lathrop

face picon face
V G wrote:
> I thought MP3 decoding was very serial in nature.

I think you're right, but that isn't the issue.  The problem is that MP3
decoding takes a lot of computes, more than a simple PIC can reasonably do
in real time.

Serial algorithms also lend themselves well to hardware implementation
because you can set up a pipeline.  Each block in the pipeline is working on
successive data, but they are all working simultaneously, something a single
CPU can't do.  A pipeline increases latency, but in the case of decoding a
MP3 stream a small delay is of no consequence as long as the overall rate
can be sustained.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000

2011\03\05@185445 by M.L.

flavicon
face
On Sat, Mar 5, 2011 at 2:28 PM, Philip Pemberton <.....piclistKILLspamspam.....philpem.me.uk> wrote:
> Although in synchronous designs (which is what FPGAs are really good
> for) it's frowned upon to use logic to generate a clock. That is, to
> have a clock driving (e.g.) a counter, then output a clock based on the
> value of that counter. The changing values can cause issues with glitches..
>

I believe the term typically used for this is "gated clock."

-- Martin K

2011\03\06@120330 by Herbert Graf

picon face
On Sat, 2011-03-05 at 19:28 +0000, Philip Pemberton wrote:
> On 05/03/11 17:02, Herbert Graf wrote:
> > That said, FPGAs have INCREDIBLE internal clock generation capabilities..
> > Most have numerous PLLs and clock dividing logic. Many have clock delay
> > blocks as well. Feed an FPGA one clock and your design can use dozens if
> > need be.
>
> Although in synchronous designs (which is what FPGAs are really good
> for) it's frowned upon to use logic to generate a clock. That is, to
> have a clock driving (e.g.) a counter, then output a clock based on the
> value of that counter. The changing values can cause issues with glitches..

You are absolutely correct, but to be clear to others, I wasn't talking
about using "the fabric".

Most FPGAs have dedicated clocking logic used to bump up or down a clock
speed, along with supplying phased clocks, and even deskewing blocks to
eliminate the input propagation delay from clock pin to logic.

I think the point both of us are making is clocking in an FPGA is
something you have to be VERY careful about, since one line of code can
have a tremendous impact on whether your design will ever function
consistently.

TTYL

2011\03\06@120526 by Herbert Graf

picon face
On Sat, 2011-03-05 at 17:58 -0500, V G wrote:
> On Sat, Mar 5, 2011 at 11:57 AM, Herbert Graf <EraseMEhkgrafspam_OUTspamTakeThisOuTgmail.com> wrote:
>
> >  > 7. Why not use a microcontroller such a PIC to do the work?
> >
> > Because the task at hand wouldn't either be possible or would be 2 slow
> > in a CPU/MCU. For example, implementing a MP3 decoder that operates in
> > real time can be very easily and cheaply implemented on a very small
> > FPGA, doing the same in a CPU/MCU would require alot more horsepower.
> >
> > Decryption is another area where the inherently parallel nature of FPGAs
> > trumps CPU/MCUs.
> >
>
> I thought MP3 decoding was very serial in nature.

It mostly is, but try writing software to decode MP3, you'll find you
need ALOT more CPU power cost wise then the amount of FPGA you'd need to
do the same task.

TTYL

2011\03\07@050817 by alan.b.pearce

face picon face
> Don't forget that they are reprogrammable, so they are upgradeable. Some
> designs may need updates or functionality changes after deployment, and
> some may need to be reconfigured regularly.
>
> If you use an ASIC, you are stuck with the initial design.

Some FPGAs are reprogrammable, some are one time program. Some boot up of an external serial EEPROM every time they are powered up, to download the programming into the FPGA.

> 3. Why are they used?

Another reason I haven't seen in an answer yet (but I haven't yet read them all) is to keep IP secret. This is probably more of a concern for complex things like encryption methods, e.g. encrypted video, where the whole process can be hidden inside the chip. Some manufacturers make FPGA chips where the programming cannot be revealed by taking the lid off and shaving the various layers to get the mask patterns. Whatever changes during programming isn't easily revealed by this method.
-- Scanned by iCritical.

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