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'[EE] Making a logic analyzer'
2011\09\20@002020 by V G

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Hi all,

I want to make a logic analyzer from either or both of my PIC32 board
(UBW32) and Xilinx Spartan 3E XC3S500E board (Nexys 2). I initially wanted
to make it to analyze the signals from my electric shaver charging station
as well as laser printer cartridge chips.

Anyway, I don't think a general purpose use logic analyzer needs to be that
fast (not for my purposes anyway).

1. The PIC32 can run up to 80MHz as far as I know. The logic analyzer will
consist of sampling as fast as it can and either streaming it to external
RAM or directly over full-speed USB to the PC. The PIC should be able to
stream at least 5Mbit/s over full-speed USB. I can safely say at least 5Msps
using this thing. Should be pretty easy for me to do.

2. The Spartan 3 can run up to 333MHz. I'm not too good with FPGAs yet, so
this will be a challenge for me. I know one can design to sample on the
rising edge AND falling edge of the clock. *Does this mean 666Msps is
possible?* Just curious. I'll probably design it to run at 10 or 20Msps
anyway. It'll then directly stream to the onboard 16M DRAM which can operate
at 80MHz in synchronous mode or 70ns time in asynchronous mode. Not too sure
about the differences yet, but I know it's more than capable of streaming in
the data. *What is the difference between asynchronous and synchronous
modes?* I googled, and didn't come up with much. I know that in synchronous
mode, the RAM is synchronized to the clock and changes occur on clock edges..
In asynchronous mode, it is "level sensitive", whatever that means, and
isn't synchronized to the clock. I've read that synchronous mode is faster,
but why? What's the concept behind it? 16MB is plenty to buffer lots of
sampling time. I could potentially code in a real time compressor to
compress logic streams where multiple samples show the same value. Should
save a lot of space and allow for much more storage. This thing also has a
high speed USB2 interface, so I could also stream the data to the computer
at high speed if I want.

Looks like I'll go with the FPGA option.

Just getting my thoughts out.

Any comments appreciated

2011\09\20@004413 by Bob Blick

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Let me be the first to introduce you to Dangerous Prototypes:
http://dangerousprototypes.com/category/logic-analyzer/

Bob

On Tuesday, September 20, 2011 12:20 AM, "V G" wrote:
{Quote hidden}

-- http://www.fastmail.fm - mmm... Fastmail...

2011\09\20@090809 by Electron

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Yes, you can sample at twice the clock speed as long as you use two banks
of RAM, and then find a way to interleave them when you need to read the
data back.


At 06.20 2011.09.20, you wrote:
{Quote hidden}

>

2011\09\20@110813 by V G

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On Tue, Sep 20, 2011 at 12:44 AM, Bob Blick <spam_OUTbobblickTakeThisOuTspamftml.net> wrote:

> Let me be the first to introduce you to Dangerous Prototypes:
> http://dangerousprototypes.com/category/logic-analyzer/
>
> Bob
>
>
You're not the first. I found it a long-ass time ago. I can't stand that
site

2011\09\20@111002 by V G

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On Tue, Sep 20, 2011 at 9:07 AM, Electron <.....electron2k4KILLspamspam@spam@infinito.it> wrote:

> Yes, you can sample at twice the clock speed as long as you use two banks
> of RAM, and then find a way to interleave them when you need to read the
> data back.
>
>
Thanks. Was just curious. I'll probably make it sample at 40Msps for now and
have it save to RAM

2011\09\20@123213 by Dwayne Reid

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At 09:07 AM 9/20/2011, V G wrote:

>You're not the first. I found it a long-ass time ago. I can't stand that
>site.

You know, VG, that you are starting to look like a really bad imitation of Olin Lathrop, except without his smarts.

You are definitely entitled to your own opinion.  However, I really don't like it when you slam somebody for no particular reason.


For what its worth, I purchased two of those little, really inexpensive 32 channel logic analyzers.  They provide astonishing performance for mere peanuts.

I've mentioned them on the PIClist previously, but here is a repeat of that information:

<copy begins>

I don't know if you have come across something called the Open-bench Logic Sniffer (OLS) but its an open-source logic analyzer based on a PIC and a FPGA.  Its good for up to 32 channels but the board itself contains only enough 5V-tolerant buffer inputs for 16 channels.  The other 16 channels are brought out to headers: you can use them directly for 3.3V signals or add on an inexpensive daughter board containing another channels of 5V-tolerant buffer.

Here's the kicker: it costs $50 including shipping to anywhere in North America (and most of the rest of the world).  Probe sets cost an extra $6 per input cable of 8 clips + ground.  The daughter-board adding 16 more buffered input channels is an extra $15.

Although the firmware is currently evolving, the current stable firmware is eminently usable.  There are two distinct software platforms available for it: SUMP and something expressly designed for the OLS by a forum member with username of jawi.

The first shipping version has FPGA code written by somebody who is not particularly experienced.  It works but the performance is less than what is actually possible.

The current beta firmware was written by somebody who actually designs large FPGA systems for a living.  He has apparently gotten almost all of the features of an Agilent HP 16550a analyzer into the unit.

Short-list of specs: single-data-rate (max) 100 MHz, double-data-rate sample rate (max)  200 MHz,

Here's the new firmware author's take on what he has done:

"My version of the fpga uses 85% of the slices, keeps the legacy triggers, meets timing easily (at 105Mhz), and adds:

Trigger Terms:
10 more 32-bit masked value comparisons.
2 range checks.
2 edge checks (rising, falling, both, neither).
2 36-bit timers (10ns to 600sec range).

States:
16 state FSM
Each state can use any combination (AND/NAND/OR/NOR/XOR/NXOR) of the trigger terms for detecting a “hit” condition, and “else” condition, or “capture” condition.

Each state also has a 20-bit hit count that must be reached before a full “hit” occurs. Hit actions include setting trigger(run),
starting/stopping timers, and advancing to the next state.

The “else” condition lets you punt to another state.

The “capture” condition lets you control what gets sampled into RAM, until you flip the trigger.

…Grab the 16550a user’s guide. I think you'll be surprised how much got squeezed in."

Overview: <dangerousprototypes.com/open-logic-sniffer/>
In-depth description: <dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer>
Even more hardware detail <dangerousprototypes.com/2010/02/25/prototype-open-logic-sniffer-logic-analyzer-2/>
Stable firmware: <dangerousprototypes.com/forum/viewtopic.php?t=1780&p=17226>
Beta firmware: <dangerousprototypes.com/forum/viewtopic.php?f=23&t=1711>
Windows software: <dangerousprototypes.com/forum/viewtopic.php?f=57&t=1198>
ordering: <http://www.seeedstudio.com/depot/open-workbench-logic-sniffer-p-612.html?cPath=174>

There is also a download available for the SUMP software - I can find that for you if you want.

Bottom line: you get a REALLY full-featured logic analyzer for peanuts.

I've been using mine since last fall and I'm thrilled with it.  I can finally retire my ancient Tek unit.

dwayne

PS - these are the same guys who designed the Bus Pirate that a lot of us have been using to do a myriad of prototyping projects with.

dwayne


-- Dwayne Reid   <dwaynerspamKILLspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax
http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

2011\09\20@131025 by John Gardner

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....Bus Pirate...

Thanks, Dwayne. Looks useful.

Jac

2011\09\20@155851 by Electron

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As I didn't have enough time to make my own, I purchased an Intronix
Logicport (which somebody from this list suggested me), and I've been
very happy so far. 34 channels, 500MHz.. not too expensive. Maybe worth
considering as an option vs to build your own.


At 18.32 2011.09.20, you wrote:
{Quote hidden}

>

2011\09\20@162302 by Isaac Marino Bavaresco

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Em 20/9/2011 16:58, Electron escreveu:
> As I didn't have enough time to make my own, I purchased an Intronix
> Logicport (which somebody from this list suggested me), and I've been
> very happy so far. 34 channels, 500MHz.. not too expensive. Maybe worth
> considering as an option vs to build your own.

How much it costs?

Isaac

2011\09\20@165245 by jim

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$400.00  to $500.00 if I remember correctly.

Jim

Regards,

Jim

{Quote hidden}

> -

2011\09\20@205029 by V G

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On Tue, Sep 20, 2011 at 12:32 PM, Dwayne Reid <@spam@dwaynerKILLspamspamplanet.eon.net>wrote:

>  You know, VG, that you are starting to look like
> a really bad imitation of Olin Lathrop, except without his smarts.
>


Everything's going as planned :)

However, note:
Smart and knowledge is two different things. Olin has knowledge. None of us
can be the judge on if he is smart or not

2011\09\21@113015 by Electron

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http://www.pctestinstruments.com/


At 22.22 2011.09.20, you wrote:
>Em 20/9/2011 16:58, Electron escreveu:
>> As I didn't have enough time to make my own, I purchased an Intronix
>> Logicport (which somebody from this list suggested me), and I've been
>> very happy so far. 34 channels, 500MHz.. not too expensive. Maybe worth
>> considering as an option vs to build your own.
>
>How much it costs?
>
>Isaac
>
>

2011\09\21@113123 by Electron

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At 02.50 2011.09.21, you wrote:
>On Tue, Sep 20, 2011 at 12:32 PM, Dwayne Reid <KILLspamdwaynerKILLspamspamplanet.eon.net>wrote:
>
>>  You know, VG, that you are starting to look like
>> a really bad imitation of Olin Lathrop, except without his smarts.
>>
>
>
>Everything's going as planned :)
>
>However, note:
>Smart and knowledge is two different things. Olin has knowledge. None of us
>can be the judge on if he is smart or not.

But you can be the judge that "Arduino is crap"? Come on..

2011\09\21@121704 by RussellMc

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> >> ... a really bad imitation of ...  without his smarts ...
....
>... crap  ...


Hat:  Where did I put it ...?

Gentlemen - please be aware of the risk of descent into personal
invective and general flaming inherent in the current discussion.

Reverting to logic analyser discussion may be wise.

Any wanting to continue current directions please change tag to [OT]
and subject line to "Your mother wears army boots" or whatever and
we'll put you on moderation from there ... :-)


Hat still not visible.

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