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'[EE] Killing a chip by measuring it'
2005\03\12@074354 by Senior Design

picon face
Quick question for you all...

How real is the threat of frying a chip simply by measuring various
values of its circuitry with a multimeter that's powered by a battery
of a higher voltage than the chip is rated to handle?

We'd built up a nice wire-wrapped circuit around an important IC and
were measuring resistances and voltage differences between different
points on our board, searching for potential shorts, etc., when we
realized that our tiny Radio Shack multimeter was powered by a 12V
battery! The chip itself operates at 3.3V and has an absolute max of
6V. Have we likely fried this thing?

Seems almost Heisenberg-ian... ruining it by measuring it...

Thanks for your help.

Julian

2005\03\12@082345 by Dan Crews

picon face
Julian,

Think about it.

Have you measured less than 1 ohm before?  

12v/1ohm = 12A !!!!!!

There's likely NO WAY that 12v battery (lithium?)  generated that much
current, and you're circuit is just fine.   The circuitry for
measuring resistance is a bit more complicated than that, and it's
likely the chip never saw 12v.   It's VERY likely nothing's been
harmed.  Most of the MM have been idiot proofed and these days you
can't even peg the meters.

In the end, you usually don't blame a fried chip because it's almost
never that (unless it got very hot, smoked, and the plastic looks
melted).  in other words, not cooked unless it looks toasty.

Dan Crews, E.I.T.
(spam_OUTcrews.danTakeThisOuTspamgmail.com)  <><

2005\03\12@084838 by Senior Design

picon face
Thanks for the response, Dan.

Your e-mail confirms an internal argument of mine that I was trying to
convince myself of.  :)  Let me be sure I understand this...

Damage done to a chip is not due to the voltage applied, but the
current induced, correct? If that's the case, then a chip will be
rated for a maximum voltage that, given the internal impedance of that
chip, a voltage beyond that rating will cause unsafe current -- IF the
voltage source is able to source the expected current. In which case,
a very high voltage (far beyond the rated max of the chip) won't
necessarily damage the chip if the induced current isn't the
"expected" result of a simple Ohm's law calculation. Right? And if
this is the case, why don't the data sheets generally specify an
absolute maximum current instead of a voltage?

Thanks!
Julian

PS. Although... when I say "fried," I guess I don't necessarily mean
toasted... can't the circuitry chip be damaged at a much lower current
without visibly ruining the entire chip?


On Sat, 12 Mar 2005 08:23:45 -0500, Dan Crews <.....crews.danKILLspamspam@spam@gmail.com> wrote:
{Quote hidden}

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2005\03\12@093729 by Dave VanHorn

flavicon
face
At 08:48 AM 3/12/2005, Senior Design wrote:
>Thanks for the response, Dan.
>
>Your e-mail confirms an internal argument of mine that I was trying to
>convince myself of.  :)  Let me be sure I understand this...
>
>Damage done to a chip is not due to the voltage applied, but the
>current induced, correct?

No.  Mosfet gate puncture is by voltage.  You leave a little crater in the
gate, and then over time, conductive fingers grow through the hole in the
glass due to the electrostatic attraction of the conductor atoms.

You can also cook things by applying too much current.


2005\03\12@100202 by Russell McMahon
face
flavicon
face
> ... convince myself of.  :)  Let me be sure I understand this...
>
> Damage done to a chip is not due to the voltage applied, but the
> current induced, correct?

A little more complex than that. There are (probably) two main failure
modes.

1.    Power dissipated causes thermal damage

2.    Voltage breaks down something which stays broken.

In the latter catefory are eg FET gates where you puncture the
extremely thin oxide layer. (Also Tantalum capacitors where you
essentially do the same thing). As many IC's are FET based they have a
very real voltage rating. You are however unlikely to get the gate
voltages in the FETs to desctruction point with a multimeter as taking
a pin outside the voltage range will probably cause the per-pin
protection diodes to conduct and provide a *reasonably* energy
resistant low impedance path. YMMV though - don't tempt fate !!! Note
that protection diodes conduct at about 0.6b outside ground or Vdd
rails WHEN POWER IS APPLIED but will conduct at far lower voltages
when no power is applied to Vdd/ground as the voltage applied to the
pin relative to ground attempts to power the IC through the protection
diode. Applying voltages to pins when power is not applied can get an
IC to go into funny modes because charge may go places it's not
designed to go. In worst case situations, more in the good old days
than now, taking a pin outside spec with power on could result int he
triggering of a parasitic thyristor relative to the IC substrate and
cause latchup and often enough destruction of the IC. This tends to
happen far less nowadays due to suitable built in protection.

SO - your chip is quite ikely OK BUT if it's not don't be totally
surprised.


> this is the case, why don't the data sheets generally specify an
> absolute maximum current instead of a voltage?

As above. Convince yourself. Get a MOSFET that you don't love too
much. Find out its rated gate voltage. Calculate a resistors value
that would allow energy far less than the FET should be able to stand
to be dissipated at this voltage. Double the resistor value. Apply a
variable voltage source gate to ground via the "safe" resistor. Exceed
Vgsmax adequately and note the FET die while gate dissipation is still
minimal.



       RM

2005\03\14@081638 by Dan Crews

picon face
Julian,

Sorry, (egg on face)  but I did oversimplify the issue quite a bit (as
others have pointed out).  That's the nice part of such a quality
group -- they won't let the simple answers go, unless they're also
dead right.

Yes, voltage is a failure mode, but protection circuitry can usually
keep some of it in check by trading SOME of the over-voltage for
current.  This shows an importance for the input's current capacity
while generating that voltage.  The typical active modes for a MM are
VERY high impedance, which means the current capacity is very low and
the voltage in the divider between input and tested resistances
usually drives the tested voltage down.  At that point, even with the
nearly infinite input impedance to a MOS gate, the protection diodes
in parallel will handle enough to keep it live.  While the protection
can't do much, but it saves a lot of bacon.

All that being said, a MM is likely to be friendly to your circuit,
but that doesn't allow for silly things like leaving MOS inputs
undefined or handling them barehanded without discharging first (here
in FL, we can get away with it in all but the worst part of winter.
High humidity can work to your benefit).  They are fragile beasts and
while they can stand more than you'd imagine, they are still as
breakable as glass.

so in the end, you'll eventually get a feel of what will and won't
damage them, and revise it as you go . . .


Dan Crews, E.I.T.
(.....crews.danKILLspamspam.....gmail.com)  <><

2005\03\14@095317 by Senior Design

picon face
Thanks for all of your help. I appreciate everyone's insight -- I
guess we'll just wait until our design is done at this point and see
how things turned out with the IC. In the mean time, I'm laying off
the 12V multimeter...

Thanks again.
Julian


On Mon, 14 Mar 2005 08:15:38 -0500, Dan Crews <EraseMEcrews.danspam_OUTspamTakeThisOuTgmail.com> wrote:
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