Searching \ for '[EE] How do I externally protect a driver FET on a' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/index.htm?key=how+externally+protect
Search entire site for: 'How do I externally protect a driver FET on a'.

Exact match. Not showing close matches.
PICList Thread
'[EE] How do I externally protect a driver FET on a'
2016\12\14@182716 by Jim Ruxton

flavicon
face

I am trying to find a way to protect the output FET in an LED driver.
Unfortunately someone else manufactures the LED driver so I don’t have
access to the inside of the box or any way to modify the FET drive
inside the box. The LED driver is being powered by a 25 Amp , 24 volt DC
external power supply. The FET is rated for fairly high current .It is a
STP100N8F6 100 Amp N Channel MOSFET . Both the driver and the output
load is being driven by the same 24 volt power supply. I want to protect
the driver against shorts across the load. I have tried various
traditional circuit breakers and PTCs. Unfortunately it appears non are
fast enough as the output FET keeps failing. I am not sure if it may be
partially because when the load is shorted this effectively shorts the
power supply through the FET. This probably causes the drive to drop to
the FET so that there is a high current through the FET while a high VDS
is forced across the FET putting it outside of it’s SOA (Safe Operating
Range) as specified in the datasheet. Does anyone have any clever ideas
as to how I can protect this FET from a load short circuit externally
without modifying the drive circuit?

Thanks,

Jim

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\14@185030 by Bob Blick

flavicon
face
Hi Jim,

The simplest thing would be to use a "smart discrete" type of device. You can get protected MOSFETs. Some are a bit expensive but save you from needing to add any new circuitry.

My internet connection is sucking right now so I can't point you to anything in particular, but all the big MOSFET players will have offerings, hopefully some will meet your specs. Some are even in traditional 3 pin packages and require no separate power supply or shunt.

Friendly regards, Bob

________________________________________
From: spam_OUTpiclist-bouncesTakeThisOuTspammit.edu <.....piclist-bouncesKILLspamspam@spam@mit.edu> on behalf of Jim Ruxton <cinetronspamKILLspampassport.ca>
Sent: Wednesday, December 14, 2016 3:27 PM
To: Microcontroller discussion list - Public.
Subject: [EE] How do I externally protect a driver FET on a device from a       short circuited load.

I am trying to find a way to protect the output FET in an LED driver.
Unfortunately someone else manufactures the LED driver so I don’t have
access to the inside of the box or any way to modify the FET drive
inside the box. The LED driver is being powered by a 25 Amp , 24 volt DC
external power supply. The FET is rated for fairly high current .It is a
STP100N8F6 100 Amp N Channel MOSFET . Both the driver and the output
load is being driven by the same 24 volt power supply. I want to protect
the driver against shorts across the load. I have tried various
traditional circuit breakers and PTCs. Unfortunately it appears non are
fast enough as the output FET keeps failing. I am not sure if it may be
partially because when the load is shorted this effectively shorts the
power supply through the FET. This probably causes the drive to drop to
the FET so that there is a high current through the FET while a high VDS
is forced across the FET putting it outside of it’s SOA (Safe Operating
Range) as specified in the datasheet. Does anyone have any clever ideas
as to how I can protect this FET from a load short circuit externally
without modifying the drive circuit?

Thanks,

Jim


-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\14@202540 by Jim Ruxton

flavicon
face
Thanks Bob,

Just to be clear I can't replace the FET that is in the enclosed driver, I need to add something externally. Do you think I could add this protected MOSFET externally which would in turn protect the internal FET in the driver?

Thanks,

Jim


On 2016-12-14 06:50 PM, Bob Blick wrote:
{Quote hidden}

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\14@214530 by RussellMc

face picon face

Bob's solution would be the easiest if it were not for the high current
involved.
Most devices of the type suggested are rated at an amp or less.
IF there are devices rated at 10's of amps anyone please advise - always
nice to know about.

Some Digikey offerings
<www.digikey.com/products/en/integrated-circuits-ics/pmic-power-distribution-switches-load-drivers/726?FV=ffe002d6&mnonly=0&newproducts=0&ColumnSort=-1120&page=1&stock=0&pbfree=0&rohs=0&k=protected+switch&quantity=&ptm=0&fid=0&pageSize=500>
max 1.1A.

About 25 of these in parallel would probably work with a little design care
and cost about $25 for the ICS BUT would "not be a preferred solution".

http://www.diodes.com/_files/datasheets/ZXMS6001N3.pdf

Turn on/off times are 40 uS max which may be slower than you need.

I used similar in an automotive environment "quaite a while" ago (20
years?)
Out of interest I tried connecting one directly across a car battery and
gating it on and off.
No problemo !.
I was duly impressed, even though it's easy enough to do with a little
thought,
That they HAD thought it through well enough (as they should have) was nice.

_________________________________

A more usual solution, and one which can be as fast as you wish, is to use
eg a MOSFET + current sense resistor + comparator.
Sub microsecond response times would be possible and probably rather slower
would be fine.

One thing to watch for is inductive spikes at turn off in circuitry which
is notionally non inductive.
With care Murphy can probably target the protection FET and the LED driver
with an inductive spike at turnoff.

A low Rdson protection FET will need minimal if any heat sinking ap[art
from PCB copper.
eg at 25A and 10 milli-Ohms Rdson = 6.25W dissipation (as above).
At 1 milliOhm Rdson its 625 mW.


I'd start with something like this

*OptiMOSTMPower-Transistor,60VIPT007N06N
<http://www.infineon.com/dgdl/IPT007N06N_Rev2.0.pdf?folderId=db3a304313b8b5a60113cee8763b02d7&fileId=db3a30433e9d5d11013e9e4618320118>*

$5.94/1 in stock Digikey.
Not as low cost as some but more suited than many.

60V, 300A, Rdson 0.785 milliOhm

62 K/W on minimum PCB footprint so COULD be run that way.
>=10V gate drive a good idea. (Abs max 20V so eg 12V good)

One to two orders of magnitude faster switching time than you need.
Drive with a suitably fast comparator using a current sense resistor.
Low Rsense = low power dissipation and lower V_Rsense so 'nicer' comparator
needed.

Hall sensor could be used - watch response times.

Suitably 'grunty' driver needed,
Gate capacitance is higher than some.



  Russell





http://www.infineon.com/dgdl/IPT007N06N_Rev2.0.pdf?folderId=db3a304313b8b5a60113cee8763b02d7&fileId=db3a30433e9d5d11013e9e4618320118




On 15 December 2016 at 11:27, Jim Ruxton <@spam@cinetronKILLspamspampassport.ca> wrote:

{Quote hidden}

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\14@225225 by Bob Blick

flavicon
face
Hi Jim,

That's a tough problem. I can't think of anything off-the-shelf.
Except perhaps just using the existing driver to drive a mechanical relay + fuse/ptc. But the low speed of a relay might not work in your application.

I'd be tempted to make something "simple" with a few discretes. But it'd be a nasty power oscillator when driving a short.

Give us a few more details and let's see what other bad ideas we can come up with :)

Cheers,
Bob

________________________________________
From: KILLspampiclist-bouncesKILLspamspammit.edu <RemoveMEpiclist-bouncesTakeThisOuTspammit.edu> on behalf of Jim Ruxton <spamBeGonecinetronspamBeGonespampassport.ca>
Sent: Wednesday, December 14, 2016 5:25 PM
To: TakeThisOuTpiclistEraseMEspamspam_OUTmit.edu
Subject: Re: [EE] How do I externally protect a driver FET on a device from a   short circuited load.

Thanks Bob,

Just to be clear I can't replace the FET that is in the enclosed driver,
I need to add something externally. Do you think I could add this
protected MOSFET externally which would in turn protect the internal FET
in the driver?

Thanks,

Jim


On 2016-12-14 06:50 PM, Bob Blick wrote:
{Quote hidden}

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\14@234110 by Brent Brown

picon face
Jim wrote:
> Just to be clear I can't replace the FET that is in the enclosed driver,
> I need to add something externally<snip>

That's harder, but not impossible.

It's quite possible that your 24V 25A supply if it's of a reasonable design has some current limiting already (e.g. say 1.5x = 38A?). As hinted at in your first post the thing causing failure may be supply droop (which could be because of said current limiting mechanism) reducing gate voltage and pushing your 100A driver FET into the linear (aka instant smoke) region. If so, then the FET could likely be encouraged to survive it (data sheet for STP100N8F6 says abs max up to 400A pulse limited by SOA, so not entirely wimpy). Adding a diode and cap to the driver supply so it stays up longer during over current events would buy you some time, but would not be a complete solution in itself.

You'd have to look at detecting the over current event (current sense resistor, drain voltage sense, supply voltage sense, or other method) and disabling the driver as quickly as possible for a satisfactorily long "cool down" period, or latch it off and require a reset, or drop out a relay to remove the fault, or activate a crowbar circuit to blow a fuse or circuit breaker, or...



-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\15@044916 by alan.b.pearce

face picon face

You haven't said what the normal current draw of each LED string is. I would be tempted to use something like a TO3 LM317 (assuming the string draw is within its current capabilities) and a resistor all mounted on a heatsink to make a current limiter for each string at about 10% higher than the normal current draw. Will get bulky for lots of LED strings, but the potential heat dissipation has to go somewhere.

If the maximum current is higher than an LM317 can handle then you are into a more complex circuit - but you could also make it do foldback so in the event of too high a current it switches that string right off to a minimal current draw.



{Quote hidden}

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\15@112632 by Jim Ruxton

flavicon
face

Thanks Bob. Yes from what I have seen the relay PTC solution would probably be too slow in this case.
Jim

On December 14, 2016 10:52:22 PM EST, Bob Blick <RemoveMEbobblickEraseMEspamEraseMEoutlook.com> wrote:
{Quote hidden}

--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\15@114247 by Jim Ruxton

flavicon
face
Thanks Russell
{Quote hidden}

Yes too bad I can't find something like above for higher currents. I would like to clamp each channel at 10 amps and the overall current to 25 amps. The unit has 5 channels. So at any time any combination of those 5 channels can use up to 25 Amps.
{Quote hidden}

Thanks for these suggestions I will look into this type of design. I think it has a lot of promise.  I have been looking at the Allegro hall effect sensors which look quite nice. Do you think I would need a PIC to do some logic ie. monitoring both current sense and voltage across VDS or do you think it could all be done analog?

Thanks again,
Jim
-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\15@114914 by Jim Ruxton

flavicon
face
Thanks Brent,


> That's harder, but not impossible.
>
> It's quite possible that your 24V 25A supply if it's of a reasonable design has some
> current limiting already (e.g. say 1.5x = 38A?). As hinted at in your first post the
> thing causing failure may be supply droop (which could be because of said current
> limiting mechanism) reducing gate voltage and pushing your 100A driver FET into
> the linear (aka instant smoke) region. If so, then the FET could likely be encouraged
> to survive it (data sheet for STP100N8F6 says abs max up to 400A pulse limited by
> SOA, so not entirely wimpy). Adding a diode and cap to the driver supply so it stays
> up longer during over current events would buy you some time, but would not be a
> complete solution in itself.
>
> You'd have to look at detecting the over current event (current sense resistor, drain
> voltage sense, supply voltage sense, or other method) and disabling the driver as
> quickly as possible for a satisfactorily long "cool down" period, or latch it off and
> require a reset, or drop out a relay to remove the fault, or activate a crowbar circuit
> to blow a fuse or circuit breaker, or...
Yes I assume the power supply is limited. It does shut off when shorted but I guess not fast enough. It's a MeanWell HLG-600H-24A power supply . I have been wondering if adding a second small power supply to keep the driver alive would help keep ithe FET out of the linear region.

Thanks again,
Jim

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\15@115520 by Jim Ruxton

flavicon
face
Thanks Alan,


> You haven't said what the normal current draw of each LED string is. I would be tempted to use something like a TO3 LM317 (assuming the string draw is within its current capabilities) and a resistor all mounted on a heatsink to make a current limiter for each string at about 10% higher than the normal current draw. Will get bulky for lots of LED strings, but the potential heat dissipation has to go somewhere.
>
> If the maximum current is higher than an LM317 can handle then you are into a more complex circuit - but you could also make it do foldback so in the event of too high a current it switches that string right off to a minimal current draw.
Looking at max current draw of 10 Amps per channel. There are 5 channels and total of 25 Amps for 5 channels. I like this solution but not sure if current limiting is enough. I have the feeling that if the FET is in it's linear region because power to the drive is failing it may not be enough? I probably have to watch voltage across the transistor too? What do you think?
Thanks again,
Jim
>

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\15@164616 by Brent Brown

picon face
{Quote hidden}

Well no need to assume.... just looked up the spec sheet for the MeanWell HLG-600H-24A and it is current limited (and is intended to be used in constant current mode for driving LED's etc without destroying them)(it really does "mean well") adjustable (internally) 12.5 - 25A.

Knowing this it seems most unlikely the supply would be delivering a current pulse capable of destroying your 100A/400A MOSFET. Yes indeed it will be well worth trying a second small power supply to keep up the driver. Would not be surprised if it then happily supplies 25A into a short circuit all day long with no ill effect.


-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\15@182504 by RussellMc

face picon face

On 16 December 2016 at 04:42, Jim Ruxton <EraseMEcinetronspamEraseMEpassport.ca> wrote:

> Thanks Russell
>
> > Hall sensor could be used - watch response times.
>
> > Suitably 'grunty' driver needed,
> > Gate capacitance is higher than some.
>


> Thanks for these suggestions I will look into this type of design. I
> think it has a lot of promise.  I have been looking at the Allegro hall
> effect sensors which look quite nice.


​At a quick glance it seems that while actual rise and fall times may be in
the microsecond range, response to field change may be 10's of us. Tghis
will depend on the specific device but may be too long deep-ending on what
is happening.  Adding a small amount of series inductance will slow the
rate of rise of current inder short circuit - and provide a subequent
increased inductive spike to be dealt with.



> Do you think I would need a PIC to
> do some logic ie. monitoring both current sense and voltage across VDS
> or do you think it could all be done analog?
>
> ​I personally wouldn't dream of using a digital interface in an
application like this until I'd convncned myself it was of high benefit.
This *should* be quite easy to do with pure analog as long as you
understand well what you want it to do. eg as people have noted, a current
limiter that sits at Imax when full voltage is applied will have an
exceedingly short lifetime.

In this case a comparator that disconnected supply when I_limit was
exceeded and then either needed manual resetting or which "tried again"
after a significant period (eg 1 second or whatever), should be enough.
"Hiccup mode" - small duty cycle PWM triggered whenever I_limit is exceeded
- may be acceptable as long as inductive spikes are dealt with and driver
has no objection to repetitive on/off powering.

If you want it any 'smarter' than that then some simple digital (1 x 74C14
hex Schmitt  inverters * usually has enough magic) or a uC might be easier
than more complex analog. Or not.



Russell

* A single hex Schmitt inverter IC can provide oscillators(s), time delays,
retriggerable and std monostables, latches , .... . An utterly amazing
amount can be done with one IC.
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\16@121010 by Jim Ruxton

flavicon
face
Thanks Brent,

       Yes I assume the power supply is limited. It does shut off when
       shorted but I guess not fast enough. It's a MeanWell
       HLG-600H-24A power supply . I have been wondering if adding a
       second small power supply to keep the driver alive would help
       keep ithe FET out of the linear region.

   Well no need to assume.... just looked up the spec sheet for the MeanWell
   HLG-600H-24A and it is current limited (and is intended to be used in constant
   current mode for driving LED's etc without destroying
   them)(it really does "mean
   well") adjustable (internally) 12.5 - 25A.

   Knowing this it seems most unlikely the supply would be delivering a current pulse
   capable of destroying your 100A/400A MOSFET. Yes indeed it will be well worth
   trying a second small power supply to keep up the driver. Would not be surprised if
   it then happily supplies 25A into a short circuit all day long with no ill effect.



I am wondering however about the fact that the voltage is directly across the drain when the load is shorted, so VDS would be 24 volts . Would this kill the device even if the driver was powered by a small supply. If I look at the SOA for the FET STP100N8F6 the 1 ms curve shows 25 Amps at about 24 volts . Does this mean I have no choice but remove the power from the FET? I can't find a spec for the time it takes the supply to shut down?
Thanks again,
Jim

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\16@122400 by Jim Ruxton

flavicon
face
Thanks Russel,





   In this case a comparator that disconnected supply when I_limit was
   exceeded and then either needed manual resetting or which "tried again"
   after a significant period (eg 1 second or whatever), should be enough.
   "Hiccup mode" - small duty cycle PWM triggered whenever I_limit is exceeded
   - may be acceptable as long as inductive spikes are dealt with and driver
   has no objection to repetitive on/off powering.

   If you want it any 'smarter' than that then some simple digital (1 x 74C14
   hex Schmitt  inverters * usually has enough magic) or a uC might be easier
   than more complex analog. Or not.





If I go this route of using a comparator etc. wouldn't it be difficult because the voltage from the power supply is unpredictable as it is shutting down. Do you feel it could be done without adding a second supply? Could I just use a ldiode followed by a large capacitor so I have some time to power the comparator when the power supply cuts out? So many moving variables here.

Thanks,
Jim
-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\16@170955 by Brent Brown

picon face
{Quote hidden}

Hi Jim,

When the load is shorted, yes the power supply is now directly connected across Drain/Source of the FET, but no, VDS will not be 24V. The FET is in the on state (around 9 milli Ohms) and the power supply will hit it's current limit of 25A. Therefore VDS is around 0.009 x 25 = 225mV. Power dissipation in the FET is 0.225 x 25 = 5.6W, well within the FETs safe operating area - for the moment.

Just to check that VDS can not be 24V, that would require 24 / 0.009 = 2667A. While brief duration high current peaks might occur if there were sufficient capacitance on the output of the supply, and the FET would be destroyed, that's likely not the case here given the supply is characterised for use in constant current mode.

The failure mechanism is probably what occurs a short time later. As the supply has been shorted (0.225V) then whatever circuitry is driving the FET gate has also lost power and the gate voltage begins to drop (relatively slowly as there'll be some capacitance in the drive electronics eg. could be some seconds or so, and assuming there are no effective under voltage lock out schemes in place and seems likely in this case there are none). The FET begins to come out of saturation (into the linear region ie the state between on and off) and RDS increases. IDS stays the same (external supply still happily current limits at 25A) so power dissipation in the FET increases proportionally with RDS, junction temperature rises at an exponential rate and very soon the FET melts and is destroyed. Can do some I2R at a few data points to illustrate:

25^2 x 0.009 = 5.6W
25^2 x 0.05 = 31W
25^2 x 0.1 = 63W
25^2 x 0.2 = 125W
25^2 x 0.5 = 313W
24^2 x 1.0 = 576W
12^2 x 2.0 = 288W

Note: Supply comes out of current limiting above max power point of  R = 0.96 Ohms (24V/25A) and power declines beyond that, but dissipation still very high and depending on time-frame SOA likely well and truly exceeded and meltdown already acheived.

Ideally: Under voltage lockout circuit to keep FET off when there insufficient gate voltage - but you're unable to modify the drive circuitry in your case.

Plan B: Separate external supply for driver circuit to keep it working when main supply drops due to short. RDS stays low, current limits at 25A, lights go out, short is removed, lights back on again - everyone is happy~!

Hope this helps.


-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\16@172750 by Van Horn, David

flavicon
face
I'd throw a scope on it and see why it's dying.

Could be it's not turning on and off fast enough?  Linear region will cause dissipation to skyrocket.
I saw a case  where a FET was dying because of extremely short (100nS) transients where the dissipation was over the limit.

Could be a voltage spike from wiring inductance exceeding VDS.

A Zener across VDS rated somewhat below the FET rating and above the power supply might help.

Scope it and see.

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\16@201905 by RussellMc

face picon face

On 17 December 2016 at 05:23, Jim Ruxton <@spam@cinetron@spam@spamspam_OUTpassport.ca> wrote:

{Quote hidden}

You can employ a 2 wire circuit (cutoff in series with load) with the
circuit powered by voltage drop across itself when on, or using an internal
power supply, butthis is less desirable for several reasons.

You very ideally use a "3 wire" cutoff circuit (eg for a low side +ve
supply version: ground, load -ve, load+ve/Vdd) then it can control what the
load 'sees' without affecting the supply.

With a 3 wire circuit, low side switch and supply +ve wrt ground.

- Break load ground lead (Vl-).
- Connect Vdd, ground, Vl- to cutoff).
- Add any desired inductive spike protection to LED driver (probably just a
reverse diode across it.

- Apply power for normal operation.
- When I_load exceeds limit load is disconnected, either until reset or for
finite period.

Load never sees high dissipation continuous-short mode as Vload is removed
fully if Iload exceeds Imax.

ie IF the problem is dissipation in the LED driver MOSFET under s/c then
removal of applied voltage and not just current limiting is required.
_______________

Fig 2 here gives an equivalent arrangement with substantially more
complexity that you would need.
They use a high side sense so IC1 is a differential amp.
Using a low side sense allows a basic comparator and reference to be used.
With a 24V supply you can use a comparator that will drive Q1 directly.

The comparator needs an added hold off / delay period after triggering to
give a 'hiccup' period, then try again.

____________________


MAX2694 application note with relevant ideas.

There are a large number of hot swap controller ICs available which prevent
over current if thge supply is short circuyited.
The 2694 has fast and slow response current set points.
Due to limited FET drive current it has turn off times typically in the
10's of us. This app note shows the addition of gate drivers to improvbe
turn off times and discusses other aspects.

https://www.maximintegrated.com/en/app-notes/index.mvp/id/2694

__________

TI LM5069 LM25061
​​
Positive High Voltage Hot Swap / Inrush Current Controller with Power
Limiting
​Product page  http://www.ti.com/product/LM5069​

​Datasheet  http://www.ti.com/lit/ds/symlink/lm5069.pdf​

​Other related products

    http://www.ti.com/product/LM5069/compare


ADM1270
http://www.electronics-eetimes.com/news/high-voltage-inrushovercurrent-input-protection-device


Again: IF the problem is dissipation in the LED driver MOSFET under s/c
then removal of applied voltage and not just current limiting is required.


    Russell
​
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\16@215537 by Sean Breheny

face picon face
100ns transients causing thermal damage? Can you describe the situation
which caused this?!

It is quite normal for the instantaneous power dissipation of a FET while
switching to be in the range of 100x to 1000x the steady state dissipation
for about 100ns. Of course, when this is averaged out it does indeed
contribute significant heating, but if you are talking about a handful of
individual transients, it would be very difficult to destroy the FET in a
few 100s of nanoseconds. Not impossible, but it would have to be a very
impressive power supply which could deliver enough current during such a
short time.

For example, the IRFS4010-7 is a FET I'm very familiar with. The
manufacturer provides a nice detailed internal thermal model. The fastest
time constant in that model is 25 microseconds. This leads to the effective
single pulse thermal resistance junction to case being 0.0007 deg C/W for a
1 microsecond pulse (the shortest they show). For a 100ns pulse, it would
be approximately 0.00007 deg C/W since we are at a timescale way faster
than the time constant so the effect scales linearly in time duration. The
steady-state value is 0.4 deg C/W

The SOA plot stops at the Vds max of 100V and at the max peak current
rating of 740A (a crazy high value for this package - the maximum
steady-state current when fully on would be something like 70A under
typical circumstances). It isn't clear what effects are driving that
(possibly current crowding/uneven current distribution within the
die/electromigration, etc.) because even at 74kW of dissipation (100V *
740A), a 100ns pulse would raise the junction temperature by only 5 deg C.
Achieving this (going from a reasonable current of say 100A to 740A and
back down again in 100ns) would be difficult without very strong gate drive
and lots of low ESR/ESL capacitance located immediately around the part.

I can believe a FET might die for non-thermal reasons (or at least not
overall junction temperature issues) in 100ns under super extreme
circumstances but not simple heat dissipation in 100ns.

Sean




On Fri, Dec 16, 2016 at 5:27 PM, Van Horn, David <
spamBeGonedavid.vanhornspamKILLspambackcountryaccess.com> wrote:

{Quote hidden}

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\16@231602 by James Cameron

flavicon
face
On Fri, Dec 16, 2016 at 09:55:34PM -0500, Sean Breheny wrote:
> 100ns transients causing thermal damage? Can you describe the situation
> which caused this?!

I've not experienced this, but I was reading Art of Electronics the other day and this kind of thing was mentioned for FETs, though the mechanism of failure was not necessarily thermal..

-- James Cameron
http://quozl.netrek.org/
-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@002532 by Sean Breheny

face picon face
My guess is that they were talking about gate punch-through or degradation
from excessive Vgs. Theoretically that's a very fast process. In practice
I've yet to see a proven case of a power MOSFET dying due to unintended
excess Vgs. I once did some experiments where I found that about 3x Vgs_max
was needed to cause instant death to a power MOSFET (take this with a
measure of salt - I think I only tested 2 devices, I was just trying to see
what would happen). I'm sure much lower could cause slow degradation over
time.

On Fri, Dec 16, 2016 at 11:15 PM, James Cameron <.....quozlspam_OUTspamlaptop.org> wrote:

{Quote hidden}

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@041941 by RussellMc

face picon face

On 17 December 2016 at 17:25, Sean Breheny <TakeThisOuTshb7.....spamTakeThisOuTcornell.edu> wrote:

> My guess is that they were talking about gate punch-through or degradation
> from excessive Vgs. Theoretically that's a very fast process. In practice
> I've yet to see a proven case of a power MOSFET dying due to unintended
> excess Vgs.


​Mechanism ​uncertain, but I had an application where FET's would fail
within minutes.
Adding gs zeners rated at > Vdrive and < Vgs max completely cured the
problem - and I've used such zeners ever since unless there is a good
reason to specifically no do so.

Trouble source was (very probably) Millar capacitance coupling of drain
transients into the gate.

In that case the load was notionally resistive but with an inductive
component. An exercise  machine load -  up to 500 Watts*, 20 kHz PWM of a
resistor loading a rectified 3 phase alternator.


      ​ Russell
​
* "Back then (about 15+ years ago) I could do 50 Watts all day, 100 Watts
probably for an hour and 500 Watts for about 10 seconds. After a burst at
500 Watts I'd need a nice lie-down :-).
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\17@100926 by Harold Hallikainen

flavicon
face
I have not been following this thread closely but saw the comment on
Miller effect. To me, Miller effect is an apparent multiplication of
capacity due to voltage amplification. Imagine we have a capacitor to
ground that has a reactance such that 1V at 1kHz yields a current into the
capacitor of 1mA. Now add an amplifier with a gain of -10 from the top of
the capacitor to the bottom (bottom of capacitor driven by amplifier
output instead of ground). Now, when we drive the top of the capacitor
with 1V, we are driving the bottom of the capacitor with -10V (10V with
phase reversed), and we have 11V across the capacitor. We now see 11mA
through the capacitor. To the voltage source, it looks like the capacitor
value has been multiplied by 11 since the current has gone up by 11 times.

Looking at Vgs, assuming an N channel FET, as Vgs increases, Vds
decreases. Capacitive coupling from the drain to the gate would decrease
Vgs, not increase it. One possibility for gate failure is inductance in
the source lead. When the FET is turned off, the gate voltage goes to zero
and the source voltage could go substantially negative due to inductance
between the source and ground. I've dealt with this by adding resistance
in series with the gate so that gate to source capacitance pulls the gate
down with the source. This does slow the circuit down, though, especially
due to the above discussed Miller capacity. You can really see this by
watching the drain voltage. When the FET is turned on by driving the gate
positive, the drain voltage will come down, but Cdg will then drive the
gate voltage down tending to turn off the FET. As I recall (it's been
years since I worked on this), the voltage drops, tends to plateau, then
drops to ground.

Good luck! I blew out a lot of FETs!

Harold



-- FCC Rules Updated Daily at http://www.hallikainen.com
Not sent from an iPhone.
-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@125057 by RussellMc

face picon face

On 18 December 2016 at 03:09, Harold Hallikainen <TakeThisOuTharoldKILLspamspamspammai.hallikainen.org
> wrote:

> I have not been following this thread closely but saw the comment on
> Miller effect.


​That was me.
'Millar' afaik - a man's name.​


> To me, Miller effect is an apparent multiplication of
> capacity due to voltage amplification.
> ​ ....​
>

​Yes. Effectively multiplication of actual Cdg by FET.
While, as you note, it's anti-phase, at least in basic effect, it leads to
increased apparent d-g coupling, and Murphy seems to be well capable of
using it for real-world activities. .
​

{Quote hidden}

​
Small series gate drive R helps, as you note.

I tried ferrite bead on FET source lead AT FET - TO220 pkg allows this
nicely.

Also GS connected reverse Schottky again mounted AT FET.
Gate oscillations not affected on +ve 1/2 cycle but claped at Vf Schottky
on negative half cycles.

BUT

Overall I found that gs connected zener, again AT FET as much as possible
to minimise interposed inductance have the best overall just-works results
and at quite low cost.

​YMMV and in some cases fancier solutions may be needed but the zener
'works a treat'.


     Russell
​
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\17@212006 by Jim Ruxton

flavicon
face

Hi Brent,

{Quote hidden}

Super helpful, so awesome of you to take the time to answer this so completely. It had slipped my mind that the current limiting would kick in forcing the voltage to drop on the power supply. Hopefully next week I will get my hands on this unit and see what happens if the driver has a secondary supply.
Cheers,
Jim
>
>

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@212251 by Jim Ruxton

flavicon
face
Thanks David,

> I'd throw a scope on it and see why it's dying.
>
> Could be it's not turning on and off fast enough?  Linear region will cause dissipation to skyrocket.
> I saw a case  where a FET was dying because of extremely short (100nS) transients where the dissipation was over the limit.
>
> Could be a voltage spike from wiring inductance exceeding VDS.
>
> A Zener across VDS rated somewhat below the FET rating and above the power supply might help.
>
> Scope it and see.
You may have missed the original post. The FET is failing when the output load is short circuited. During normal operation the fETs are switching fine and all works perfectly.
Cheers,
Jim

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@213159 by Jim Ruxton

flavicon
face
Thanks Harold,

{Quote hidden}

Really appreciate the clear explanation of some of the mechanisms behind what is going on inside the FET and the Miller effect. Hopefully it will help me in blowing less FETs :)
Jim

-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

2016\12\17@213825 by Jim Ruxton

flavicon
face

Hi Russell,

{Quote hidden}

Yes I always have a small gate resistor on my drive circuits  but the GS
Zener never. Thanks a lot for that hint. Definitely look at implementing
that in the future as an insurance policy. What voltage value of Zener
would you typically use ?
Jim

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\17@214649 by Jim Ruxton

flavicon
face

Thanks Russell,
Wow lots of great information below. I'll look at the links you have
provided and see if any of those hot swap IC's can be useful in my case.
So amazed by the knowledge and generosity by everyone on this list.
Much thanks,
Jim
{Quote hidden}

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\18@000501 by RussellMc

face picon face

> Overall I found that gs connected zener, again AT FET as much as possible
>
> to minimise interposed inductance have the best overall just-works results
>
> and at quite low cost.
>
>
>
> ​YMMV and in some cases fancier solutions may be needed but the zener
>
> 'works a treat'.
>

On 18 December 2016 at 14:38, Jim Ruxton <.....cinetronspamRemoveMEpassport.ca> wrote:

> Yes I always have a small gate resistor on my drive circuits  but the GS
>
Zener never. Thanks a lot for that hint. Definitely look at implementing
> that in the future as an insurance policy. What voltage value of Zener
> would you typically use ?
>
> ​As low as practical while being enough avove the gata drive waveform so
as to never conduct signigicantly ​when gate drive is high.
eg with 12V gate drive and a Vgsmax = 20V+ FET, somewhere around 15V is
probably about right.


        Russell
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\18@035056 by Sean Breheny

face picon face

One thing to bear in mind when it comes to gate zener clamps is that
hard-switched FETs will display significant inductive effects due to source
lead inductance. This can mean, for example, that just because you see a
20V spike in Vgs doesn't actually mean that the gate oxide is subjected to
20V. If you have a FET with a Kelvin connection to the source (or at least
multiple source leads) then you can place the clamp between the gate and
that Kelvin or pseudo-Kelvin connection, but placing it across the entire
gate-source node pair may be clamping unnecessarily. I still insist on
seeing a measured Vgs which never exceeds the rating, but I do not demand
much margin because simulation and analysis show that the actual voltage
stress inside the FET is less than what is measured due to source
inductance.

I've been designing FET-based motor drives in the 1kW power range for more
than 10 years. I have >100k units in the field. We have had a few failures
which were never explained fully, but no epidemic, and I have not used
zener clamps in any of them. I have recently begun using ferrite beads in
the gate connection, at the suggestion of a co-worker, and I was surprised
to see that they can help with EMI generated by the motor drive. Surprised
because I would have thought they would saturate at less than the peak gate
drive current (and surprised for a few other reasons, too).

On Sun, Dec 18, 2016 at 12:04 AM, RussellMc <RemoveMEapptechnzspamspamBeGonegmail.com> wrote:

{Quote hidden}

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\18@041955 by RussellMc

face picon face

On 18 December 2016 at 20:50, Sean Breheny <TakeThisOuTshb7spamspamcornell.edu> wrote:

> One thing to bear in mind when it comes to gate zener clamps is that
> hard-switched FETs will display significant inductive effects due to source
> lead inductance. This can mean, for example, that just because you see a
> 20V spike in Vgs doesn't actually mean that the gate oxide is subjected to
> 20V. If you have a FET with a Kelvin connection to the source (or at least
> multiple source leads) then you can place the clamp between the gate and
> that Kelvin or pseudo-Kelvin connection, but placing it across the entire
> gate-source node pair may be clamping unnecessarily.


​In my case the key metric was "worked essentially perfectly, cost almost
nothing".
I think that design was produced in the 10's of thousands range  - but I
cannot be sure as there were royalties due and some exceedingly [+]
suspect production volume returns after ​the ciient's wife got hand-on
involved. But adding a zener changed a "fail in minutes" arrangement to
"fail never. It was PWM ing a more or less resistive load across a somewhat
filtered rectified DC from a user driven 3 phase alternator, so lots of
room for Murphy to play.

​As you note, not much zener margin needed below Vgsmax - and enough above
Vdrive max as to have relatively minor effect on drive. ​


​  Russell
​
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist

2016\12\19@104653 by Van Horn, David

flavicon
face

100ns transients causing thermal damage? Can you describe the situation which caused this?!

The situation was a poorly designed H bridge that was spontaneously igniting it's PCB.
The FETs had no pull resistors, and no protection against software caused shoot-through, but those turned out not to be the problem.
While the design of the H bridge was poor for those reasons, I could not actually see any cases where the FETS were being put into shoot-thru, but the boards would still fail while being measured.
Looking deeper, I used a voltage probe and current probe to look at the instantaneous dissipation on the FETs, and found that they were being taken outside their SOA for short periods.
This happened very frequently (10's of kHz) and the dissipation on the FETs was already pretty high. Talking with ST who made the FETs, we agreed that they should have a look, and I sent them samples that had been run a long time but hadn't started the failure cascade.
They found that the die had somewhat decoupled from the epoxy, which in turn lowered their ability to get rid of heat.
Only some devices would fail this way, most could stand the abuse.

>From there, the problem gets interesting.  The cumulative damage eventually caused catastrophic failure in the FETs, but the SMPS kept delivering power to the board, in "Hiccup" mode.
Each pulse delivered about 1W to the board, and eventually (hours) the FET would crater.
After cratering, the FET would heat the PCB further and deposit conductive debris on the board.
Over time (hours) the failure would propagate down to the PCB, and start a carbon arc.
The PCB designer was not a fan of ground planes, possibly due to the rather primitive PCB software he was fond of, which made planes a real pain to use, so the board was not able to dissipate the heat before the next pulse.
So the temperature rises.  Eventually, the flammable gases would accumulate in the enclosure and it would chuff and flames would exit the case.
This could go on for hours, with the power supply dutifully hiccupping along.
For a good read on this sort of failure, google "Low Voltage, the incompetent ignition source"
If you got lucky, a particular board might hit the resistance range that looks like a legitimate load to the power supply, taking it out of hiccup mode and into full power, delivering 70+ watts.


I replaced those devices with larger devices with better SOA, and also added lockouts in hardware for shoot through, and a few other safeguards.
In the end, it was a trivial boost in cost, and it got rid of the problem.
The new hardware controls power to the bridge instead of leaving it powered constantly, and also measures all the FETs before engaging power to drive the motor.
Once motion is done, the bridge is powered down.


-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
mailman.mit.edu/mailman/listinfo/piclist
.

More... (looser matching)
- Last day of these posts
- In 2016 , 2017 only
- Today
- New search...