>
> This is probably a very basic question, but it is troubling me.
>
> In my robot's design, I have a couple of daughterboards running PICs (or
> maybe other uC's). I want to design a circuit for supplying power to the
> daugherboards.
>
> The main power source is a battery pack that supplies 12V. What I'm trying
> to decide is whether I design one extra daughterboard for voltage
> regulation
> or if I include voltage regulation in each one of the daughterboards.
> Here's
> what I see as advantages and disadvantes of each method, please critique.
>
> One VReg
> ========
> Advantages:
> - savings in real estate
> - savings in power consumption
> Disadvantages:
> - If I install a diode or a bridge rectifier on the
> daughterboard, I won't have 5V for the electronics
> because of the v.drop of the diodes
> - If one of the daughterboards needs 3.3V instead of 5V,
> I will need a vreg on the daughterboard anyway
>
> Distributed VRegs
> =================
> Advantages:
> - Each board is encapsulated, which means I can connect
> any voltage (in between vreg specified min and max) that it
> will work
> - I can select a specific vreg for each board according to its
> characteristics (current and voltage needs)
> - I may choose a vreg with overvoltage and overcurrent features
> - I can implement the reverse polarity diode before the vreg,
> therefore the diode voltage drop won't affect the voltage
> available for the load
> Disadvantages
> - real estate
> - power consumption
>
> (cost is not really a problem... this is not going to production)
>
>
> Cheers
>
> Padu
>
>

>-----Original Message-----
>From: piclist-bouncesKILLspammit.edu [.....piclist-bouncesKILLspam.....mit.edu]
>Sent: 02 November 2005 09:06
>To: Microcontroller discussion list - Public.
>Subject: Re: [EE] Help deciding on voltage regulation
>
>
>On 11/2/05, Olin Lathrop <EraseMEolin_piclistspam_OUTTakeThisOuTembedinc.com> wrote:
>> Padu wrote:
>> >> I might put a decent buck regulator on the main board
>that produces
>> >> about 5.5 volts, then distribute that to each daughter board.
>> >
>> > Do you have any suggestions on which one?
>> >
>> > I liked the idea, since there is a big step down from 12V
>to 5V and
>> > energy is very precious in my application.
>>
>> My knee jerk reaction is something like the 5.5V power supply of the
>> QuickProto-01 (http://www.embedinc.com/products).  You can see it on
>> page two of the schematic at
>> http://www.embedinc.com/products/qprot01/qprot2.pdf.
>
>Olin,
>sheet2/7 from this design it's a very good prove about what is
>happening if a good software PIC programmer is designing hardware...
>
>Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
>
>cheers,
>Vasile

> I guess you have little experience of driving power MOSFETs in high
> frequency switching applications?
>
> The driver needs to have a high current capability in order to
> charge/discharge the (significant) gate capacitance of the MOSFET to
> minimise the time spent in the linear region.  Failure to do this
> results in poor efficiency and high power dissipation.  A single NPN
> with resistive collector load does not (usualy) satisfy these
> requirements unless the resistor has a very low value, which again
> increases power dissipation and reduces efficiency.

> The reduction by one transistor is unlikely to be worthwhile.
> R4 can be increased until speed becomes an issue - which may be at 2K
> as that's what Olin's used.
>
> ******************   BUT   *******************
>
>                 as shown this circuit has a major problem.
>
> Vgs_max for the IRF7416 is -20 volts and when supply voltage is much
> above 20 volts the FET will be driven into a potentially (pun almost
> intended) fatal state.

> Vasile Surducan wrote:
> >> You can see it on page two of the schematic at
> >> www.embedinc.com/products/qprot01/qprot2.pdf.
> >
> > sheet2/7 from this design it's a very good prove about what is
> > happening if a good software PIC programmer is designing hardware...
>
> Actually I'm a hardware designer that does a lot of software/firmware too.
>
> > Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
>
> I looked at it sideways, upside down, and inside out and I don't see
> redundancy.  These three transistors together take the ground-referenced GP2
> PIC output and cause it to drive the gate of the high side FET Q3.  In other
> words, they form a high side FET driver.
>
> The 0-5V PIC output drives the base of Q6.  R9 on the emitter causes the
> collector of Q6 to act like a switchable current sink.  Assume Q6 has a
> 700mV B-E drop, then the emitter current will be (5.0V - 700mv) / 750ohms =
> 5.7mA.  Q6 has pretty decent gain, so this is basically the current that
> will be sunk by its collector when the PIC pin is high.  This current causes
> a voltage accross R4, which is 2Kohms.  5.7mA x 2Kohms = 11.5V.  So the
> bottom end of R4 will be at the input supply rail when the PIC GP2 output is
> low, and 11.5V below that rail when the PIC output is high.  Q2 and Q4 are
> both emitter followers.  These provide much higher current drive for the
> signal on the low side of R4.  This lower impedence signal drives the gate
> of Q3.  The reason for lowering the impedence from 2Kohms to about 20-40
> ohms is to overcome the considerable effective capacitance of the FET gate
> quickly.  A little voltage is lost in the process, but the FET gate will
> still be driven with about 11V, which is plenty to solidly turn on that FET.
> R5 is there to make sure the FET is off on startup and to eventually bring
> the FET gate to 0 (with respect to the FET source) when nothing is going on.
>
> C11 on the emitter of Q6 sharpens the edges of the current sink.  When the
> PIC output goes high, the emitter current is much higher than the 5.7mA
> steady state for a short time.  This is just enough time at higher current
> to overcome the other capacitances on R4 and the bases of Q2 and Q4 and the
> wiring to bring the bottom side of R4 to its on level quickly.  Once there
> the steady state current thru R9 takes over and maintains it there.  The
> 100pF value of C11 was determined experimentally since it is impossible to
> calculate all the parasitic capacitance effects.  C11 also helps at turn
> off.  Bipolar transistors are slowest at turning off since charge lingers in
> the base until used up by causing collector current.  When the PIC output is
> brought low, the B-E junction is actually reversed biased for a very short
> time causing some of the base charge to be actively sucked out turning the
> transistor off quickly.
>
> Do you still think Q6, Q4, and Q2 are redundant?  If so, show me an
> alternative for a low side PIC to drive a high side P-channel FET gate.

> On 11/2/05, Olin Lathrop <RemoveMEolin_piclistTakeThisOuTembedinc.com> wrote:
> > Vasile Surducan wrote:
> > >> You can see it on page two of the schematic at
> > >> www.embedinc.com/products/qprot01/qprot2.pdf.
> > >
> > > sheet2/7 from this design it's a very good prove about what is
> > > happening if a good software PIC programmer is designing hardware...
> >
> > Actually I'm a hardware designer that does a lot of software/firmware too.
> >
> > > Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
> >
> > I looked at it sideways, upside down, and inside out and I don't see
> > redundancy.  These three transistors together take the ground-referenced GP2
> > PIC output and cause it to drive the gate of the high side FET Q3.  In other
> > words, they form a high side FET driver.
> >
> > The 0-5V PIC output drives the base of Q6.  R9 on the emitter causes the
> > collector of Q6 to act like a switchable current sink.  Assume Q6 has a
> > 700mV B-E drop, then the emitter current will be (5.0V - 700mv) / 750ohms =
> > 5.7mA.  Q6 has pretty decent gain, so this is basically the current that
> > will be sunk by its collector when the PIC pin is high.  This current causes
> > a voltage accross R4, which is 2Kohms.  5.7mA x 2Kohms = 11.5V.  So the
> > bottom end of R4 will be at the input supply rail when the PIC GP2 output is
> > low, and 11.5V below that rail when the PIC output is high.  Q2 and Q4 are
> > both emitter followers.  These provide much higher current drive for the
> > signal on the low side of R4.  This lower impedence signal drives the gate
> > of Q3.  The reason for lowering the impedence from 2Kohms to about 20-40
> > ohms is to overcome the considerable effective capacitance of the FET gate
> > quickly.  A little voltage is lost in the process, but the FET gate will
> > still be driven with about 11V, which is plenty to solidly turn on that FET.
> > R5 is there to make sure the FET is off on startup and to eventually bring
> > the FET gate to 0 (with respect to the FET source) when nothing is going on.
> >
> > C11 on the emitter of Q6 sharpens the edges of the current sink.  When the
> > PIC output goes high, the emitter current is much higher than the 5.7mA
> > steady state for a short time.  This is just enough time at higher current
> > to overcome the other capacitances on R4 and the bases of Q2 and Q4 and the
> > wiring to bring the bottom side of R4 to its on level quickly.  Once there
> > the steady state current thru R9 takes over and maintains it there.  The
> > 100pF value of C11 was determined experimentally since it is impossible to
> > calculate all the parasitic capacitance effects.  C11 also helps at turn
> > off.  Bipolar transistors are slowest at turning off since charge lingers in
> > the base until used up by causing collector current.  When the PIC output is
> > brought low, the B-E junction is actually reversed biased for a very short
> > time causing some of the base charge to be actively sucked out turning the
> > transistor off quickly.
> >
> > Do you still think Q6, Q4, and Q2 are redundant?  If so, show me an
> > alternative for a low side PIC to drive a high side P-channel FET gate.
>
> Maybe we should start with naming the most important parameter which
> has never been mentioned here: which is the switching frequency and
> which is the maximum current load? I can guess is not so high as
> Russel believes (see the inductance value which is quite big and
> dimensioned at max 1.6A that shows a continous current less than
> 0.5...0.8A, but also there are two huge capacitors Q9 and Q10 with low
> ESR which are drawing a lot of ripple current). I think the schematic
> it does not need such big engineering in driving the power FET.
> Compute how big is the 2K * Ciss compared with the switching time
> (which is producing Q3 dissipation). Ciss is about 2nF at a switching
> frequency of about 1MHz and Vgs=0V (I doubt you can switch Q3 from
> PIC10F at this frequency, so probably it's less than half). So the
> estimated time constant Tau is about 4 microseconds, does the
> 4microseconds switching delay killing your FET ?
> R4 and C11 could dissapears. Instead those two a resistor in the Q6
> base. If need a switching acceleration scheme could be there in the
> base of Q6. I bet the schematic is working the same without Q2 and Q4
> if you choose the correct Vgsoff for the Q3 (maybe you need another
> small resistor between the lower end of R4 and the Q6 colector if
> indeed you're supplying this at 30V, IRF7416 has an VGS of +/-20V and
> an VBRDSS of 30V)
> I presume the real supply never excedeed 15-20V. Also if the Q3 it's
> packed in SO8 package, than have only 2.5W maximum dissipated power.
> So it's not a power supply.