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'[EE] Ground plane inductance'
2007\02\07@155850 by

Hi all,

I have a circuit involving FETs switching 50 amps. The FETs are driven
by a gate driver IC which has two supply voltages, one which is for
the logic side and the other for the drive side.

When a FET switches on, an inductive spike develops between the source
lead and various parts of the ground plane, due to the really high
di/dt (it switches on in about 150 nanoseconds). To minimize turn-on
time, I locate the drive-side driver ground reference very close to
the source lead. However, the reference for the logic side has to be
with the logic circuits. The spec on the IC says that there can be no
more than 5V between the two references, so this means that I must
make sure that the inductive spike is no greater than 5V. I have had
ICs die for apparently this reason (latch-up).

To minimize the spike, I am using film caps close to each FET source
to return the current to the positive supply rail (where it ultimately
comes from). There are also bulk electrolytic caps to prevent the
current spikes from going back to the battery. Here's my problem: in
order to properly place and size the caps, I need to be able to
estimate the inductance between two points on the ground plane.
Simulation shows that this makes a big difference.

I can find all kinds of formulas and calculators online for
inductance, but I cannot find a copper sheet inductance formula.

I even found a reference from Dr. Howard Johnson saying that one
cannot calculate the inductance of a ground plane, only of a wire OVER
a ground plane.

I think he is right if it is a perfect ground plane, but his comment
doesn't apply to a real, thin copper sheet.

Certainly, my circuit is ALSO a closed loop (the current is not just
in the plane but in wires and components, too), but I do not care
about the TOTAL inductance, only that between two points on the plane.

Any ideas?

Thanks,

Sean
>
>
> Any ideas?

Tie some reasonable C across it, and measure ringing frequency, and solve
for inductance?
Sean Breheny wrote:
> Hi all,
> ...
> To minimize the spike, I am using film caps close to each FET
> source to return the current to the positive supply rail (where it
> ultimately comes from). There are also bulk electrolytic caps to
> prevent the current spikes from going back to the battery. Here's
> my problem: in order to properly place and size the caps, I need
> to be able to estimate the inductance between two points on the
> ground plane. Simulation shows that this makes a big difference.
>
> I can find all kinds of formulas and calculators online for
> inductance, but I cannot find a copper sheet inductance formula.
>
> Any ideas?
>
> Thanks,
>
> Sean

I've heard http://www.mwoffice.com/ can do what you want.

Regards,
Dennis.

This is my first post in a long time as I've only just re-subscribed.

Hi Sean,

Does your application require the FETs to be switched so quickly?

My first thought (if possible) was to eliminate the cause of the problem
by slowing the switching rather than filtering the effect?

Regards,

Nigel

Sean Breheny wrote:
{Quote hidden}

>
>
> Does your application require the FETs to be switched so quickly?
>
> My first thought (if possible) was to eliminate the cause of the problem
> by slowing the switching rather than filtering the effect?

I was thinking the same thing, but I assumed that he'd thought of that.

Interesting things happen when flinging high currents around fast, and
heavily layout dependent.
> The spec on the IC says that there can be no
> more than 5V between the two references, so this means that I must
> make sure that the inductive spike is no greater than 5V. I have had
> ICs die for apparently this reason (latch-up).

Wouldn't it be a good idea to use an optocoupler (6N137) to isolate the
two circuits?

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu

> Wouldn't it be a good idea to use an optocoupler (6N137) to isolate the
> two circuits?

Would you like to buy a bridge to go along with that 150ns 6N137 ?

:) Cheerful regards,

Bob

Hi Dave,

The problem is that I am just laying out the board now. I need to
determine how much inductance to expect. I guess if I had to I could
hack something up to make some measurements, though.

Sean

On 2/7/07, David VanHorn <dvanhornmicrobrix.com> wrote:
> >
> >
> > Any ideas?
>
>
> Tie some reasonable C across it, and measure ringing frequency, and solve
> for inductance?
> -
Yes, it does. The Rds of these FETs is so low (5 milliohms) that
switching losses dominate i2R losses for any slower speed (and then I
would have thermal problems).

On 2/7/07, David VanHorn <dvanhornmicrobrix.com> wrote:
{Quote hidden}

> -
On 2/7/07, Sean Breheny <shb7cornell.edu> wrote:
>
> Hi Dave,
>
> The problem is that I am just laying out the board now. I need to
> determine how much inductance to expect. I guess if I had to I could
> hack something up to make some measurements, though.

I'd like to see a schematic and layout on this one.
It could be very nasty.
Sean Breheny wrote:
> Hi Dave,
>
> The problem is that I am just laying out the board now. I need to
> determine how much inductance to expect. I guess if I had to I could
> hack something up to make some measurements, though.
>
> Sean
>
> On 2/7/07, David VanHorn <dvanhornmicrobrix.com> wrote:
>
>>> Any ideas?
>>>
>> Tie some reasonable C across it, and measure ringing frequency, and solve
>> for inductance?
>> --
Well, I did an experiment. I rigged up a little circuit with a FET and
a cap to put 30 amp pulses with a 2.5 usec rise time through a section
of copper plane. I measured the rise time with a 20MHz, 100A current
probe, and I scoped two points on the plane in differential mode on my
scope, at 100MHz BW.

The answer I came out with was about 20 to 30 nH per inch, which
sounds plausible but sadly, higher than I was hoping. This was 4oz
copper, but my guess is that the copper thickness doesn't change this
much because of skin effect.

Thanks for the suggestion, Bob. I will probably be using 3 or 4 oz
copper, actually, both for the thermal properties and for the
electrical ones.

I'm beginning to see that the ultra-low Rds ON specs for FETs are not
all they are cracked up to be. Even if your Rds is tiny, you still can
have great trouble trying to get the power dissipation low due to
switching losses (this is a 20kHz PWM, 100A three-phase motor driver.
It is 50A per FET with two FETs in parallel.)

Dennis, thanks for the mwoffice suggestion. That may help long-term
but I just wanted to try to get a quick, rough answer for this.

Thanks all,

Sean
>
>
> The answer I came out with was about 20 to 30 nH per inch, which
> sounds plausible but sadly, higher than I was hoping. This was 4oz
> copper, but my guess is that the copper thickness doesn't change this
> much because of skin effect.

Right, it will become important later, when the on time allows for some
heating.

You might look at your turn-on time, and see if some small gate resistance
improves things.
You can get inductive effects in the source lead where the fet actually
turns on and off a few times because of the dI/dT on the source lead.
The trick is to get the fet to turn on as fast as it really can, and no
faster.

The turn off bears watching too, I'd drop some 1kV parts in there, and check
for spikes that would avalanche you.  You won't see them with lower voltage
parts.
On 2/7/07, Bob Blick <bblicksonic.net> wrote:
>
> > Wouldn't it be a good idea to use an optocoupler (6N137) to isolate the
> > two circuits?
>
> Would you like to buy a bridge to go along with that 150ns 6N137 ?
>
> :) Cheerful regards,
>
> Bob
>

Would an HCPL-3120 do the job?  I've had good success with the 3140 in
a lower-current application.

http://rocky.digikey.com/WebLib/Agilent/Web%20Data/HCNW3120_HCPL-J312,3120.pdf

Regards,
Mark
markrages@gmail
--
You think that it is a secret, but it never has been one.
>
>
>
> Would an HCPL-3120 do the job?  I've had good success with the 3140 in
> a lower-current application.
>
>
> http://rocky.digikey.com/WebLib/Agilent/Web%20Data/HCNW3120_HCPL-J312,3120.pdf

To turn on a fet fast, you need amps.
On 2/7/07, David VanHorn <dvanhornmicrobrix.com> wrote:
> >
> > Would an HCPL-3120 do the job?  I've had good success with the 3140 in
> > a lower-current application.
> >
> >
> > http://rocky.digikey.com/WebLib/Agilent/Web%20Data/HCNW3120_HCPL-J312,3120.pdf
>
>
> To turn on a fet fast, you need amps.

That part provides 2A.  How many are needed?  Sean, how many coulombs

Regards,
Mark
markrages@gmail
--
You think that it is a secret, but it never has been one.
> Would you like to buy a bridge to go along with that 150ns 6N137 ?

The Brooklyn bridge? If the price is OK...

A 6N137 is quite a bit faster than 150 ns, and even faster optos are
available.

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu

On 2/7/07, Sean Breheny <shb7cornell.edu> wrote:
> Hi all,
>
> I have a circuit involving FETs switching 50 amps. The FETs are driven
> by a gate driver IC which has two supply voltages, one which is for
> the logic side and the other for the drive side.
>
> When a FET switches on, an inductive spike develops between the source
> lead and various parts of the ground plane, due to the really high
> di/dt (it switches on in about 150 nanoseconds).

How did you've measured those spikes as long it's about various ground
plane where you've connect the scope probe's ground ?

This is solved easily with  a ferite core mounted directly on the FET source.
http://www.steward.com/pdfs/emi/technical/Use%20of%20Ferrites%20in%20EMI.pdf

To minimize turn-on
> time, I locate the drive-side driver ground reference very close to
> the source lead. However, the reference for the logic side has to be
> with the logic circuits. The spec on the IC says that there can be no
> more than 5V between the two references, so this means that I must
> make sure that the inductive spike is no greater than 5V. I have had
> ICs die for apparently this reason (latch-up).

If you had spikes greater than 5V then you have a poor PCB design, no doubt.

>
> To minimize the spike, I am using film caps close to each FET source
> to return the current to the positive supply rail (where it ultimately
> comes from).

How many, what values,  and how they are positioned on the PCB ?

There are also bulk electrolytic caps to prevent the
> current spikes from going back to the battery.

Battery has lower impedance than any electrolytic, so a large PCB
route it's enough.

Here's my problem: in
> order to properly place and size the caps, I need to be able to
> estimate the inductance between two points on the ground plane.

Parctically impossible. Theoreticaly would be fine.

> Simulation shows that this makes a big difference.

Simulation = double zero.

{Quote hidden}

> -
>> The problem is that I am just laying out the board now. I need to
>> determine how much inductance to expect. I guess if I had to I could
>> hack something up to make some measurements, though.
>
>I'd like to see a schematic and layout on this one.
>It could be very nasty.

Sounds to me more like a case of making sure there is a single point ground
attachment between the two systems, and keeping the power rails in separate
areas. Proper earthing rules need to be stringently applied to stop the high
current ground bounce getting back into the logic circuitry - and dealing
with the gate drive will be another exciting part of this, meaning there are
three items that all need to meet at the grounding point.

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