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'[EE] FT2232H USB Avalon Core'
2011\11\14@081956 by Yigit Turgut

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Hi all,

Original hardware IC provides 480MB/s and the core provides 25MB/s.
20MB/s is enough for me now thus I decided to give the core a go since
XC3S500E will be on the board already with %~45 unused core.

http://opencores.org/project,ft2232hcore

I used it as a part a design in ISE 13.2 and it seems to occupy 2
cores (with 11inputs,+6outputs). It's a spartan .

Anyone tried it ? I am trying to shrink it to 1 core do you think it
is worth to effort ?  Also XC3S500E supports 620Mb/s per I/O, thus
achieving 480Mb/s seems to be possible to me ?

Have a nice day.

Yigi

2011\11\14@090119 by V G

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On Mon, Nov 14, 2011 at 8:19 AM, Yigit Turgut <spam_OUTy.turgutTakeThisOuTspamgmail.com> wrote:

> Hi all,
>
> Original hardware IC provides 480MB/s and the core provides 25MB/s.
> 20MB/s is enough for me now thus I decided to give the core a go since
> XC3S500E will be on the board already with %~45 unused core.
>
> http://opencores.org/project,ft2232hcore
>
> I used it as a part a design in ISE 13.2 and it seems to occupy 2
> cores (with 11inputs,+6outputs). It's a spartan .
>
> Anyone tried it ? I am trying to shrink it to 1 core do you think it
> is worth to effort ?  Also XC3S500E supports 620Mb/s per I/O, thus
> achieving 480Mb/s seems to be possible to me ?
>
> Have a nice day.


Excellent. I did not know this existed. I don't understand, what do you
mean by "occupy 2 cores"?

Also, what is the IO standard used for USB2.0? I know it's differential
signalling, but is it LVDS

2011\11\14@091207 by V G

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On Mon, Nov 14, 2011 at 9:01 AM, V G <.....x.solarwind.xKILLspamspam@spam@gmail.com> wrote:

{Quote hidden}

Nevermind. I got excited for a sec thinking this was an actual FT232H logic
on FPGA but all I see is usb_sync.vhd which looks pretty useless to me. Is
it just meant to interface WITH the FT232H physical chip? If so, that
doesn't look hard at all and I don't understand why it would need an entry
in opencores...

Anyway, I have a XC3S500E as well. I don't see why you wouldn't be able to
get 480Mb/s. Use a 240MHz clock and sample on both edges I guess and hope
your timing report allows that speed for your design

2011\11\14@095055 by Yigit Turgut

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Yes, I thought the same but it turned out that it's just to interface
with the actual chip. It partially works but that is useless to me. It
would be great if it was FT232H logic FPGA. Which is also possible as
well.

Clock is 200MHz for now and will correspond to 400mb/s approximately.
WIl try and report.

On Mon, Nov 14, 2011 at 12:11 PM, V G <.....x.solarwind.xKILLspamspam.....gmail.com> wrote:
{Quote hidden}

>

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