> >
> www.reddit.com/r/ECE/comments/s1nai/anyone_know_of_fpgas_that_plug_directly_into_the/
> > http://www.drccomputer.com/pdfs/DRC_Accelium_Coprocessors.pdf (pdf)
>
> Of interest (to me at least) is that the data  transfer rate
> capabilities of these devices so far exceeds the current requirements
> of the vast majority of still-image applications that Moore's law is
> liable to make such capabilities affordable before they become too
> slow. ie we can look forward (one can hope) to affordable photo data
> handling rates that exceed the capability of the top camera sensors
> when they become so ludicrously capable that sensor resolutions exceed
> the capability of "reality" to provide the image data.  Good dream any
> way :-). A RAW files occupies around 1 to 3 megabytes per megapixel.
> so when/if we get to 300 Mp sensors (!) you need 1 GB/s transfer rates
> to handle 1 RAW-image/second.
>
> The Accelium processor would thus handle data externally at 15 images
> second at 1 GB/image and around 300 x 1 GB images per second
> internally.
> A 300 mP image is about 21,000 x 14000 pixels on will allow a print of
> about 6 foot x 4 foot at 300 dpi.
>
> That was based on an upper size RAW file - you cou;d probably produce
> a 12 foot x 8 foot image from an extremely high quality JPEG at 300
> dpi with that sort of image size.
> ie about big enough to shoot billboard sized images at 300 dpi.
>
> For an A4 source image the resolution is about 15 micrometres per
> pixel - ie this is beyond what wedding photographers are going to
> "need" for portraits anytime soon.
>
>