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'[EE] FPGA or CPLD?'
2007\01\29@233758 by Paul Anderson

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Here's a pretty basic question for the list.  What is the difference
between an FPGA and a CPLD?

--
Paul Anderson
VE3HOP
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"May the electromotive force be with you."

2007\01\30@002233 by Forrest W Christian

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Paul Anderson wrote:

>Here's a pretty basic question for the list.  What is the difference
>between an FPGA and a CPLD?
>  
>
That's a hard question to answer since the line is becoming more and
more blurred (see the MachXO we were discussing earlier).  I'm also not
a FPGA expert by any means.

FPGA=Lots of gates-10K on up, millions is not uncommon.   Typically but
not always volatile - I.E. needs external flash to load it's "program",
which takes a bit (not immediate on).

CPLD= typically onboard flash, immediate startup, relatively small
numbers of gates  (1000 is pretty typical).

Generally, a FPGA has enough gates that you can implement an entire
system in it.   Many FPGA manufacturers now have entire software
microprocessor cores which run within the FPGA itself, where a typical
CPLD is useful for glue only.

CPLDs seem to also have a more ridgid internal structure, whereas the
FPGA is more flexible in it's signal routing internally.

Not sure if this helps but I really typically think of the CPLD as a PAL
on steroids, and the FPGA as a programmable ASIC.

The MachXO I mentioned is one of those beasts where you can really think
of it as a small FPGA with the cost and nonvolatility benefits of a CPLD.

-forrest


2007\01\30@050529 by Mike Harrison

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On Mon, 29 Jan 2007 22:20:28 -0700, you wrote:

{Quote hidden}

Another common comparison is 'granularity' - an FPGA is closer to a sea of gates, with each gate
being fairly simple , e.g. a 4-input lookup table or single register..
CPLDs typically contain a number of more complex macrocells - typically one or 2 registers with
various internal routing options, with programmable interconnect between them.

Larger FPGAs also often contain blocks of RAM - often dual-port, plus other useful blocks like
multipliers.


2007\01\30@101655 by alan smith

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Field Programmable Gate Array - a sea of gates, where you have look up tables, or LUTs or macrocells that contain a set if 'gates' and support like an ALU, memory elements, etc.  Timing is not predictable, since the routing can be all over the place unless you define parameters, etc.  New devices have built in clock synthesis and management (back when I did my first FPGA, nothing like that was available).
 
 Complex Programmable Logic Device - came from the old PAL and PLDs, sort of a combination of the two in some ways.  Most if not all are flash based, moved away from OTP, EEPROM and PEEL except for legacy and some rad hard devices.  Timing is predictable since the routing channels are more fixed than a FPGA.  CPLDs are great for replacing glue logic or doing simple functions, but they really don't do math other than building your own ALU internally.
 
 Small CPLDs are pretty cheap, and run very low power (at low frequencies...read the fine print on the coolrunner devices) for the smaller devices.  As you increase in density and I/O count, the FPGA becomes a suitable subsitute since the price increases to the point of smallish FPGA's.   FPGA's can do anything a CPLD can do, other than predictable timing, but the same is generally not true for the CPLD.  But remember you might need external memory for the FPGA, depending on your choice of device.
 
 New devices from the major players are putting the programming flash internal to the FPGA for both speed of programming and security (no bitstream to capture).  Some have had  those internal for some time (Actel).  Lattice is new in the game of FPGA's having taken what was once the ORCA line of devices, but has always been a major player in the CPLD arena.  In fact, they may be the last one doing the good old 22V10.
 
 You can also run both hard and soft cores inside the larger FPGA's.  Softcores are homegrown processors, that you build within the toolkits.  Altera has the NEOS, Xilinx has the microblaze.  Both (I know Xilinx for sure) are 32 bit processors, and you can add mostly free perphrials such as I2C, SPI, UARTs, memory controllers or even create your own.  Hard cores include ARM, PowerPC and 8051 like devices.  There are also PIC cores running around as well.


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2007\01\30@104311 by Herbert Graf

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On Mon, 2007-01-29 at 23:37 -0500, Paul Anderson wrote:
> Here's a pretty basic question for the list.  What is the difference
> between an FPGA and a CPLD?

The difference used to be very well defined, these days it's getting a
little fuzzy.

You can get some insight from the naming:
CPLD - Complex Programmable Logic Device
FPGA - Field Programmable Gate Array

>From the naming you can see that CPLDs tend to be a little more
"complex". The "blocks" (they have various names, macrocell is common)
generally have a relatively large amount of logic in them. This is both
good and bad. If your logic maps nicely into a macrocell you can pack a
surprising amount of logic in these parts. If your logic doesn't map
nicely you can easily run out of space.

CPLDs generally are smaller in "gate count" then FPGAs, have lower pin
counts, usually have a few hobbyist friendlyish packages (PLCC) and
often can't run as fast. That said, they are usually cheaper and easier
to use (they hold their configuration with power off, most FPGAs need
external PROMs to hold the configuration which is then bootstrapped on
powerup) and are less complicated in power requirements (usually single
rail if you select a device whose core voltage matches your IO voltage,
otherwise typically two rails).

FPGAs OTOH are more "simple" in nature. Their "blocks" (often called
slices) usually only have a LUT or two, a few flops and maybe some
inverters. That said they have alot of these slices, meaning they are
more general; more logic will have a chance of an efficient mapping then
on a CPLD.

They are generally larger, both in gate count and physical size then
CPLDs. Packages generally range from hobbyist unfriendly (TQFP) to
nearly hobbyist impossible (BGA). Their configuration memory is usually
SRAM, meaning you need to load the config on every power cycle (either
through JTAG or through PROMs or other bootstrapping solutions). Larger
parts often need multiple PROMs, which can really start eating board
space. There are some FPGAs these days with FLASH for configuration
memory, but that's relatively rare, and never on the largest parts.
Power generally is at least two rails (typically one for the core, at
least one for IO, sometimes one for another internal rail). If you are
running multiple IO voltages you'll need a rail for each bank that runs
at the different voltage.

If you are new to programmable logic I recommend starting with CPLDs.
They are "big enough" for the typical beginner projects and are easier
to handle (compile times are in the seconds, pin counts are lower,
cheaper).

A simple example of "useful" code that easily fits in a small CPLD is in
my logan project:

http://repatch.dyndns.org:8383/pic_stuff/logan

This was a project I built a few years ago using a 16F877 for most of
the control, and a CPLD for address generation, strobe generation and
clock switching. The code for the CPLD can be found in the
logic_analyzer.v file.

Hope this helped. TTYL



2007\01\31@173449 by k n

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On the subject of FPGA's and CPLD's, does anyone know of an FPGA that is
either:
-Easy to use for a hobbyist (DIP Packaging?)
or
-Comes on a PCB with all (or most) of the pins going to headers or pins
I have simulated a few designs using VHDL and ModelSim, but the thought of
soldering a 100 pin TQFP chip doesn't seem doable.

Paul Anderson wrote:
>Here's a pretty basic question for the list. What is the difference
>between an FPGA and a CPLD?

2007\01\31@180131 by Robert Young

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> -----Original Message-----
> From: .....piclist-bouncesKILLspamspam@spam@mit.edu
> [piclist-bouncesspamKILLspammit.edu] On Behalf Of k n
> Sent: Wednesday, January 31, 2007 4:35 PM
> To: .....piclistKILLspamspam.....mit.edu
> Subject: Re: [EE] FPGA or CPLD?
>
>
> On the subject of FPGA's and CPLD's, does anyone know of an
> FPGA that is
> either:
> -Easy to use for a hobbyist (DIP Packaging?)
> or
> -Comes on a PCB with all (or most) of the pins going to
> headers or pins I have simulated a few designs using VHDL and
> ModelSim, but the thought of soldering a 100 pin TQFP chip
> doesn't seem doable.
>

Don't know of any current production CPLDs still in DIP package.  There
are 22V10s and assorted PALs around in DIP though...

Go checkout Jean's stuff at fpga4fun.com.  He has some nice modules that
might fit your needs.

Rob

2007\01\31@233337 by Herbert Graf

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On Wed, 2007-01-31 at 17:01 -0600, Robert Young wrote:
> > On the subject of FPGA's and CPLD's, does anyone know of an
> > FPGA that is
> > either:
> > -Easy to use for a hobbyist (DIP Packaging?)
> > or
> > -Comes on a PCB with all (or most) of the pins going to
> > headers or pins I have simulated a few designs using VHDL and
> > ModelSim, but the thought of soldering a 100 pin TQFP chip
> > doesn't seem doable.
> >
>
> Don't know of any current production CPLDs still in DIP package.  There
> are 22V10s and assorted PALs around in DIP though...

With regards to CPLDs: PLCC packages are good for hobbyists since you
can get through hole PLCC sockets on 0.1" centers. Not a perfect
solution, but definitely doable, and cheaper then buying boards.

The Xilinx 9536 and 9572 CPLDs both come in 44 pin PLCC packages. There
are many others.

TTYL




'[EE] FPGA or CPLD?'
2007\02\01@024601 by Tobias Gogolin
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>soldering a 100 pin TQFP chip doesn't seem doable.

Soldering TQFP  or PQFP is not a problem...
as long as the pins are straight and the board well made (ideally bearing
tined soldermasked pads)
Solder and adjust 2-4 pins then
just roll a solderiron controlled miniwave of fresh solder (/w internally
flux) down (using gravity) each side
finally inspect with microscope or magnifier...



On 1/31/07, k n <EraseMEknlistspam_OUTspamTakeThisOuTgmail.com> wrote:
{Quote hidden}

> -

2007\02\01@041617 by Mike Harrison

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On Wed, 31 Jan 2007 23:33:35 -0500, you wrote:

{Quote hidden}

These FPGA DIL modules will be available soon :
www.enterpoint.co.uk/component_replacements/craignell.html
Rumour is these will be pretty low cost

There are also these, but a bit expensive :
http://shop.trenz-electronic.de/catalog/product_info.php?products_id=81


The biggest CPLD device I know of in a true DIL is Atmel's ATV2500, but this needs a programmer.


2007\02\11@071802 by Hector Martin

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Tobias Gogolin wrote:
>> soldering a 100 pin TQFP chip doesn't seem doable.
>
> Soldering TQFP  or PQFP is not a problem...
> as long as the pins are straight and the board well made (ideally bearing
> tined soldermasked pads)
> Solder and adjust 2-4 pins then
> just roll a solderiron controlled miniwave of fresh solder (/w internally
> flux) down (using gravity) each side
> finally inspect with microscope or magnifier...

My method usually runs more like so: tack opposite pins and center
device, then run soldering iron adding solder (and bridging pins more
often than not), then clean up using desoldering braid. Works decently :)

Or you could do it the better way, and use solder paste. I've done PLCC
etc using manually-applied solder paste (just drawing lines around the
chip, ignoring the individual pads), and it tends to work quite well
with few bridges if you apply just the right amount. However, using a
mask is of course much better. Then, you either use hot air, or bake the
PCB using an oven or a skillet. The guys at sparkfun.com have a bunch of
nice tutorials on different methods for soldering SMT devices.

--
Hector Martin (hectorspamspam_OUTmarcansoft.com)
Public Key: http://www.marcansoft.com/marcan.asc

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