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'[EE] FPGA Metrics'
2007\06\18@120716 by Herbert Graf

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On Sun, 2007-06-17 at 17:32 -0700, Tobias Gogolin wrote:
> I'm as always keeping a watch on the accessibility of FPGA for my
> experimental circuits from easy to order sources such as digikey.com or
> mouser.com
> And I recently noticed that there are now quite a few good offers in the
> $20-40 range even with up to 500k gates
> In comparison are all the big offers such as Xilinx. Latticesemi, Altera and
> Actel
> However some say gate equivalents some logic units and who knows what else
> ...
> How do these numbers relate and why?

Unfortunately they don't.

It's similar to trying to compare the amount of program memory for one
MCU vs. another with a completely different architecture, 4kbyte of
program memory on an 8bit PIC is not the same as 4kbyte of program
memory on an ARM.

The industry standard is usually a count of how many 2 input NAND gates
you can squeeze into an FPGA. Unfortunately most FPGAs have LUTs far
bigger then 2 inputs (and even then a 2 input LUT can contain more then
1 NAND gate in functionality, i.e. an XOR), so this count isn't of much
use beyond a "factor of magnitude" number.

The problem is different FPGAs have different architectures, meaning one
piece of code may map much more efficiently in one FPGA vs. another.

Even worse is the WAY you write your could can change things (i.e. how
you encode your state machines, how many flops you use, etc.), along
with how important timing is to you (a design aiming for fastest speed
will need more logic then one designed for smallest size).

And it's not just FPGAs from different companies having different
capacities, even FPGAs from the same company can be drastically
different in how they are able to map your code.

As a result of all this, FPGA manufacturers don't even bother trying to
standardize between each other, it's frustrating, but just the way it
is. Some manufacturers DO give you a very rough idea of how to compare
between their own FPGAs. For example, a Xilinx Vertex 4 LX40 has about
twice the capacity of a Virtex 2 Pro 20, in a VERY rough way.

The only way to REALLY tell is you just put your code through the tools
and see how many LUTs you use.

Depending on your code, a better way to tell sometimes is to see how
many flops you use. The synthesizers are VERY good at optimizing
combinational logic, so it's common to see very large device utilization
fluctuation between parts on combinational logic. Flops OTOH aren't
something you can really optimize away (aside from say tying a TESTEN
pin low in the compile), so flop counts should be very similar between
tools. Unfortunately it's very rare to be limited by flop counts in an
FPGA (unless you use funky memories that can't be inferred as block
rams, in which case you can easily blow away your flop count. This isn't
a good idea though since using that many flops really kills your
timing).

To start off with I'd try putting your code through the tools and see
which part it'll fit into. Then get a part twice the size. If you don't
have code, go for a part "in the middle" size wise, it'll probably end
up being WAY to big, but you can optimize that later.

As for me, I've mostly used Xilinx parts and do recommend them. They
have a version of their software that's free to use for many of the
smaller parts.

Good luck! TTYL

2007\06\18@120716 by Herbert Graf

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On Sun, 2007-06-17 at 17:32 -0700, Tobias Gogolin wrote:
> I'm as always keeping a watch on the accessibility of FPGA for my
> experimental circuits from easy to order sources such as digikey.com or
> mouser.com
> And I recently noticed that there are now quite a few good offers in the
> $20-40 range even with up to 500k gates
> In comparison are all the big offers such as Xilinx. Latticesemi, Altera and
> Actel
> However some say gate equivalents some logic units and who knows what else
> ...
> How do these numbers relate and why?

Unfortunately they don't.

It's similar to trying to compare the amount of program memory for one
MCU vs. another with a completely different architecture, 4kbyte of
program memory on an 8bit PIC is not the same as 4kbyte of program
memory on an ARM.

The industry standard is usually a count of how many 2 input NAND gates
you can squeeze into an FPGA. Unfortunately most FPGAs have LUTs far
bigger then 2 inputs (and even then a 2 input LUT can contain more then
1 NAND gate in functionality, i.e. an XOR), so this count isn't of much
use beyond a "factor of magnitude" number.

The problem is different FPGAs have different architectures, meaning one
piece of code may map much more efficiently in one FPGA vs. another.

Even worse is the WAY you write your could can change things (i.e. how
you encode your state machines, how many flops you use, etc.), along
with how important timing is to you (a design aiming for fastest speed
will need more logic then one designed for smallest size).

And it's not just FPGAs from different companies having different
capacities, even FPGAs from the same company can be drastically
different in how they are able to map your code.

As a result of all this, FPGA manufacturers don't even bother trying to
standardize between each other, it's frustrating, but just the way it
is. Some manufacturers DO give you a very rough idea of how to compare
between their own FPGAs. For example, a Xilinx Vertex 4 LX40 has about
twice the capacity of a Virtex 2 Pro 20, in a VERY rough way.

The only way to REALLY tell is you just put your code through the tools
and see how many LUTs you use.

Depending on your code, a better way to tell sometimes is to see how
many flops you use. The synthesizers are VERY good at optimizing
combinational logic, so it's common to see very large device utilization
fluctuation between parts on combinational logic. Flops OTOH aren't
something you can really optimize away (aside from say tying a TESTEN
pin low in the compile), so flop counts should be very similar between
tools. Unfortunately it's very rare to be limited by flop counts in an
FPGA (unless you use funky memories that can't be inferred as block
rams, in which case you can easily blow away your flop count. This isn't
a good idea though since using that many flops really kills your
timing).

To start off with I'd try putting your code through the tools and see
which part it'll fit into. Then get a part twice the size. If you don't
have code, go for a part "in the middle" size wise, it'll probably end
up being WAY to big, but you can optimize that later.

As for me, I've mostly used Xilinx parts and do recommend them. They
have a version of their software that's free to use for many of the
smaller parts.

Good luck! TTYL

2007\06\20@183444 by Tobias Gogolin

picon face
Thanks Herbert for this very complete answer!
Part of the reason for me asking was that I was comparing Altera
EP1C12 with 12k LU?
to a Xilinx Spartan 3E at 500k gates?
and Actel ProAsic3 at 400k Gate functions...
And Lattice I don't remember, exactly but I think the number was in
the Altera Range
And at least for Altera and Xylinx I remember that the CMOS feature
size was similar, well at least the voltage should be a good indicator
for that right?
1.5 -1.8 Volt, which brings me to another question: They probably like
a similar switching power supply like for the CPU's on modern
motherboards, right? Any recommendations as far an easy to implement
solution there (ok other than a 1.5 V battery)?

cheers

Tobias


On 6/18/07, Herbert Graf <spam_OUTmailinglist3TakeThisOuTspamfarcite.net> wrote:
{Quote hidden}

> -

2007\06\20@191027 by Herbert Graf

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On Wed, 2007-06-20 at 15:34 -0700, Tobias Gogolin wrote:
> Thanks Herbert for this very complete answer!
> Part of the reason for me asking was that I was comparing Altera
> EP1C12 with 12k LU?
> to a Xilinx Spartan 3E at 500k gates?
> and Actel ProAsic3 at 400k Gate functions...
> And Lattice I don't remember, exactly but I think the number was in
> the Altera Range
> And at least for Altera and Xylinx I remember that the CMOS feature
> size was similar, well at least the voltage should be a good indicator
> for that right?
> 1.5 -1.8 Volt, which brings me to another question: They probably like
> a similar switching power supply like for the CPU's on modern
> motherboards, right? Any recommendations as far an easy to implement
> solution there (ok other than a 1.5 V battery)?

Most of the FPGA tools have a "power estimator" tool that will tell you
how many watts you need to supply.

If you're relatively slow then power will be pretty minimal, say a watt
at most. If you're running fast (and have alot of code) you can easily
get into the 10s of watts range on some of the larger parts.

As for power supply, each will need a few rails. At minimum there's
usually a core supply in the 1-2V range, then there's at least one IO
supply for each IO standard you need to drive (i.e. if you are driving
3.3 and 2.5V parts you'd have a supply for each, and the appropriate
banks voltage inputs tied to the appropriate supply). Some parts have
additional supplies for other things (i.e. the configuration section
usually needs it's own voltage, usually a "standard" one like 3.3V).

The only supply that you have to be really careful of is the core
supply. The FPGA can source 20A or more of this supply if you run enough
at a fast enough speed. Most vendors give "recommended" supply designs,
and that's what I've always followed (sometimes with modifications to
reduce size or capacity if I know I won't be drawing that much power).
You are correct in that they are very closely related to CPU supplies,
and most of the reference supply designs I've seen used chips meant for
the CPU market (IIRC the supply I used for a Virtex 4 part actually has
VID pins that are designed to change the voltage level; these pins
usually connect directly to a CPU which is how the CPU can set it's
voltage).

Note that I usually deal with very large FPGAs, for the mid range it's
likely things are "simpler", although power wise I don't see things
being that different (unless you're barely using any of the capacity of
the FPGA I doubt you'd get away with using a linear supply for Vcore).
The IO and other low amperage supplies I usually either already have on
my board, or just throw a linear part down.

Good luck! TTYL

2007\06\21@014230 by Tobias Gogolin
picon face
Thanks again Herbert!
searching my email for FPGA metrics I'm also looking at my copy of the
java optimized
processor (core) list, where the question of power consumption was on
around January this Year... (http://groups.yahoo.com/group/java-processor/)

the consensus was obviously frequency dependency - quiescent state or
asynchronous operation constituting exceptions...
that's another reason I like FPGAs cause such a thing as combinatorial
asynchronous designs is theoretically possible!

This brings me to another question!
what is the lowest cost FPGA infrastructure that is runtime reprogrammable?

None of those I mentioned, true?



>
> On 6/18/07, Herbert Graf <.....mailinglist3KILLspamspam@spam@farcite.net> wrote:
Most of the FPGA tools have a "power estimator" tool that will tell you
how many watts you need to supply.

If you're relatively slow then power will be pretty minimal, say a watt
at most. If you're running fast (and have alot of code) you can easily
get into the 10s of watts range on some of the larger parts.

As for power supply, each will need a few rails. At minimum there's
usually a core supply in the 1-2V range, then there's at least one IO
supply for each IO standard you need to drive (i.e. if you are driving
3.3 and 2.5V parts you'd have a supply for each, and the appropriate
banks voltage inputs tied to the appropriate supply). Some parts have
additional supplies for other things (i.e. the configuration section
usually needs it's own voltage, usually a "standard" one like 3.3V).

The only supply that you have to be really careful of is the core
supply. The FPGA can source 20A or more of this supply if you run enough
at a fast enough speed. Most vendors give "recommended" supply designs,
and that's what I've always followed (sometimes with modifications to
reduce size or capacity if I know I won't be drawing that much power).
You are correct in that they are very closely related to CPU supplies,
and most of the reference supply designs I've seen used chips meant for
the CPU market (IIRC the supply I used for a Virtex 4 part actually has
VID pins that are designed to change the voltage level; these pins
usually connect directly to a CPU which is how the CPU can set it's
voltage).

Note that I usually deal with very large FPGAs, for the mid range it's
likely things are "simpler", although power wise I don't see things
being that different (unless you're barely using any of the capacity of
the FPGA I doubt you'd get away with using a linear supply for Vcore).
The IO and other low amperage supplies I usually either already have on
my board, or just throw a linear part down.

2007\06\22@110139 by Herbert Graf

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face
On Wed, 2007-06-20 at 22:42 -0700, Tobias Gogolin wrote:
> Thanks again Herbert!
> searching my email for FPGA metrics I'm also looking at my copy of the
> java optimized
> processor (core) list, where the question of power consumption was on
> around January this Year... (http://groups.yahoo.com/group/java-processor/)
>
> the consensus was obviously frequency dependency - quiescent state or
> asynchronous operation constituting exceptions...
> that's another reason I like FPGAs cause such a thing as combinatorial
> asynchronous designs is theoretically possible!
>
> This brings me to another question!
> what is the lowest cost FPGA infrastructure that is runtime reprogrammable?

Hmm, now that's a good question. I have looked into remotely
programmable options, but have always settled on either logging into a
PC remotely connected to the board through a JTAG cable, or using a
systemace type solution (the projects I work on are prototype project
with very low volumes).

SystemAce is an asic from Xilinx which allows you to program an FPGA
from a flash card. It has an MCU port on it that I believe allows you to
reprogram the card through an MCU (never needed this functionality so I
haven't tried it), so that is an option.

Otherwise unfortunately I don't know of any other solutions.

Thanks, TTYL

2007\06\22@132820 by Dave Tweed

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On Wed, 2007-06-20 at 22:42 -0700, Tobias Gogolin wrote:
> This brings me to another question!
> what is the lowest cost FPGA infrastructure that is runtime reprogrammable?

I'm not sure exactly what you're asking, but SRAM-based FPGAs are the
lowest cost (per gate equivalent), since they don't need the extra
processing steps to support flash cells (or whatever).

Any SRAM-based FPGA can be (re)configured from any microprocessor,
either through its JTAG port or directly through its PROM interface
(by bit-banging, if necessary). You just need to have enough memory
on the micro to hold the FPGA bitmap(s) you want to use. I'm most
familiar with Xilinx products, for which this is well documented,
but I'm sure all the other SRAM-based FPGA vendors support similar
functionality.

Partial reconfiguration, in which other parts of the FPGA continue to
function during the process, is a more complex question. Not all FPGA
families support this, and I believe it can only be done through the
JTAG interface on those that do.

-- Dave Tweed

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