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'[EE] FF edge polarity'
2004\10\06@103319 by Wouter van Ooijen

face picon face
asked on sci.electronics.design, but no real answer yet. let's ask here:

I am confused about the edge on which a FF triggers. My intuition would
say that any logic symbol with a plain wedgie (no inverting blob) should
trigger on the positive edge, but maybe that's too simple.

H&H 2nd edition P508/509 states that a JK triggers on the negative edge,
and an edge-triggered FF on the positive edge. But it is not clear
whether that refers to the implementation as shown, or to the bare logic
symbol. Most JK symbols do have the inverting blob on the clock input.

P510 suggests that both dividers behave the same, which would imply that
the plain JK symbol triggers on the negative edge, yet P511 states that
the shown ripple divider clocks on the negative edge, the JK symbols do
have the inverting blob, so the plain JK symbol would clock on the
positive edge.

My tentative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF? Positive,
neative, or worse: there is no standard?

Wouter van Ooijen

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Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
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2004\10\06@105800 by Bob Ammerman

picon face
I have never seen a JK that clocked on the positive edge.

Bob Ammerman
RAm Systems

----- Original Message -----
From: "Wouter van Ooijen" <spam_OUTwouterTakeThisOuTspamvoti.nl>
To: "'Microcontroller discussion list - Public.'" <.....piclistKILLspamspam@spam@mit.edu>
Sent: Wednesday, October 06, 2004 10:33 AM
Subject: [EE] FF edge polarity


{Quote hidden}

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2004\10\06@110003 by Mike Hord

picon face
Check page 511.  There it shows a four-bit counter, composed of
"blob-clocked" JK FF's.  The action there occurs on the falling edge,
which indicates to me that "no-blob" JK FF's should trigger on the
rising edge.

BUT, and this is a very big but, even if there is a "standard", recall
that standards usually aren't.  Consider any discussion of RS-232
ports, and all the caveats and such that arise around those.

For the final word, I would:
A.  Always check the data sheet.
B.  Go back to the logic circuit for a JK FF and see whether that
inversion is inherent, or if it is added later on.  IIRC (it's been a few
years since I last discussed the internals of a JK), that bubble is
inherent in the design, but is moved outside to make it more
obvious to the reader that the signal is negative-triggering.

I hope I did more than further muddy the waters.  This thread should
be VERY educational.

Mike H.

On Wed, 6 Oct 2004 16:33:18 +0200, Wouter van Ooijen <obf> wrote:
{Quote hidden}

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2004\10\06@113337 by Spehro Pefhany

picon face
At 10:55 AM 10/6/2004 -0400, you wrote:
>I have never seen a JK that clocked on the positive edge.

CD4027B, for one.

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speffspamKILLspaminterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com




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2004\10\06@113840 by Alan B. Pearce

face picon face
>My tentative conclusion is that a plain (no inverting
>blob) D FF clocks on the positive edge. But on which
>edge clocks a plain JK FF? Positive, neative, or
>worse: there is no standard?

I am not sure there is a standard for edge triggers. I do seem to recall
symbols that show arrows on the clock line to signify if it is + or -
trigger. However I don't think that fits the IEC symbols.

Right - to settle this in my own mind, I went and got the company copy of BS
EN 60617-12:1999, which is also the equiv IEC standard (or more correctly,
the other way round). Part 12, Binary logic elements has a symbol listed as
12-07-07 (ascii art below)


  +---
  |
---|>
  |
  +---

which is "dynamic input - the (transitory) internal 1 state corresponds to
the transition from the external 0 state to the external 1 state. At all
other times the internal logic state is 0" i.e. positive edge clocked. Note
that this specifically refers to the "positive logic state" so if your logic
is such that +5V = logic 0 and 0V = logic 1 then the positive edge clock is
the one going from +5v to 0v.

Then there is the version with the circle in the line outside the box which
is classed as negative edge clocked (using a similar verbose description)

Then there is the version with a half arrow on the external line, which
means that "direct polarity" convention is being used and inverted, rather
than logic state convention. As far as I can work out from section 6.3 of
the same standard, the arrow means that the polarity convention is inverted,
as distinct from the logic convention. The standard quite clearly states
that only one of the inversion styles is to be used within a diagram.

Not sure if this helps make it clearer. :))

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2004\10\06@113946 by Wouter van Ooijen

face picon face
> I have never seen a JK that clocked on the positive edge.

I did not ask for a real JK, just the symbol. The ones you saw, did the
symbol have an inverting blob outside the rectangle? If so, the chip
would indeed be negative edge triggered, but the bare symbol (without
the blob) would be positive edge triggered?

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu


>
> Bob Ammerman
> RAm Systems
>
> {Original Message removed}

2004\10\06@114018 by Alan B. Pearce

face picon face
>I have never seen a JK that clocked on the positive edge.

This may be because internally they are a master-slave FF. The master
latches the input state on the +ve edge, the slave clocks the outputs on
the -ve edge.

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2004\10\06@114137 by Wouter van Ooijen

face picon face
> For the final word, I would: (snip)

I am looking for the answer to give to my students. There are of course
two parts:
1- the symbol *should* indicate ....
2- in the real world, do check the datasheet

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu


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2004\10\06@133529 by William Chops Westfield

face picon face

On Oct 6, 2004, at 7:55 AM, Bob Ammerman wrote:

> I have never seen a JK that clocked on the positive edge.
>
My ancient understanding is that the JK flipflops are master/slave
things, and not explicitly "edge triggered"; rather the inputs are
"read" when the clock is high, and the outputs change when the clock
is low.  So the interesting stuff happens at the high->low transition.
A modern data sheet talked about edges, though, so I dunno...

BillW

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2004\10\06@142949 by Peter L. Peres

picon face

On Wed, 6 Oct 2004, Wouter van Ooijen wrote:

> asked on sci.electronics.design, but no real answer yet. let's ask here:

The symbol *must* reflect the real behavior of the part. However there are
some old databooks where the clock input of a JK flipflop is figured
without the inverting circle. The text however says it triggers on the
negative edge.

Peter

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2004\10\06@162143 by Roland

flavicon
face
Hi
I always understood that the symbol below meant edge-triggered, or rather,
that the transtition is time sensitive because of the pulse shortening
interns of the flip flop. A long rise/fall time and it doesn't work.

So this will 'only trigger on a rising edge being X nano seconds maximum
duration'
>   +---
>   |
>---|>
>   |
>   +---

and this simply means, 'only trigger on a falling edge being X nano seconds
maximum duration'
>   +---
>   |
>--O|>
>   |
>   +---
where X is defined on the data sheet;


Regards
Roland Jollivet

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2004\10\06@165405 by Wouter van Ooijen

face picon face
> My ancient understanding is that the JK flipflops are master/slave
> things, and not explicitly "edge triggered"; rather the inputs are
> "read" when the clock is high, and the outputs change when the clock
> is low.  So the interesting stuff happens at the high->low transition.
> A modern data sheet talked about edges, though, so I dunno...

That was my understanding too: A FF is just two latches in a
master/slave arrangement, with inverted clock for the second latch.
Total effect is 'remembering' the input value at the edge. But various
people seem to be convinced that a JK FF is two edge-sensitove FF's (not
latches) toed together, so it would remember the value at one edge, only
to show it at the output at the other edge. Seems a waste of transistors
to me, but maybe this is how it realy is?

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu


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