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'[EE] AND-OR-AND - simplest implementation?'
2004\10\14@160757 by Denny Esterline

picon face
I need a simple logic function, a two input AND feeding a two input OR
feeding another two input AND [see picture]. Since I don't need any other
logic in the project I hate waste the space and use two chips, is anyone
else's Boolean algebra less rusty that mine? Is there a one part
implementation (other than a PAL or CPLD)?

Thanks
-Denny


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*'';HX8?2!00`.P``
`
end

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2004\10\14@164829 by Mauricio Jancic

flavicon
face
Look in here

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/trangate.html

regards

Mauricio Jancic
Janso Desarrollos
Microchip Consultant Program Member
(54) 11-4542-3519
spam_OUTinfoTakeThisOuTspamjanso.com.ar
http://www.janso.com.ar


>>{Original Message removed}

2004\10\14@165557 by Herbert Graf

flavicon
face
On Thu, 2004-10-14 at 16:12, Denny Esterline wrote:
> I need a simple logic function, a two input AND feeding a two input OR
> feeding another two input AND [see picture]. Since I don't need any other
> logic in the project I hate waste the space and use two chips, is anyone
> else's Boolean algebra less rusty that mine? Is there a one part
> implementation (other than a PAL or CPLD)?

What about a PIC? A 12F629 could do the same. TTYL

-----------------------------
Herbert's PIC Stuff:
http://repatch.dyndns.org:8383/pic_stuff/

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2004\10\14@170623 by Eisermann, Phil [Ridg/CO]

flavicon
face
piclist-bounces@mit.edu wrote:
> I need a simple logic function, a two input AND feeding a two input OR
> feeding another two input AND [see picture]. Since I don't need any
> other logic in the project I hate waste the space and use two chips,
> is anyone else's Boolean algebra less rusty that mine? Is there a one
> part implementation (other than a PAL or CPLD)?
>

umm. a PIC <vbg>

seriously, though. I don't see anything simpler than D[AB+C] e.g. the
circuit you have shown. The only 'trick' i remember off the top of my
head would be the old 'decoder as a minterm generator', but that was
already old way back when I was young :) Do they still teach that in
school? In any case it makes no sense in this application.

Unless you can 'design-out' the need for the logic function?
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2004\10\14@170831 by James Newtons Massmind

face picon face
If you inputs are A, B (going to the first AND) C (additional input to the
OR) and D (additional input to the last AND) then your diagram is:

Out = ( A * B + C ) * D

Using a 4 gate NAND chip, you can get

Out = /( A * B + C ) * D

In other words, the exact same thing, but with the output inverted or you
can get

Out = ( A * B + /C ) * D


The tricks are:
- An AND gate with both inputs and the output inverted works just like an
OR.
- A NAND gate with both inputs tied together acts like an inverter.

NAND Input
Gate a  b  Output
---- -- -- ------
1   A  B  2a
2   1o C  3a
3   2o D  4a & 4b
4   3o 3o Output = ( A * B + /C ) * D

NAND Input
Gate a  b  Output
---- -- -- ------
1   A  B  2a
2   1o 4o 3a
3   2o D  Output = /( A * B + C ) * D
4   C  C  2b


Another option (if you can find the chip) is a 7456 Dual AND-OR-INVERT gate.
http://focus.ti.com/lit/ds/sdls113/sdls113.pdf

It does Out = /(a * b + c * d) and has two of them. Actually, I don't think
that can do what you need... Hummm... Well, I hope that helps.

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> {Original Message removed}

2004\10\14@171419 by Denny Esterline

picon face
> On Thu, 2004-10-14 at 16:12, Denny Esterline wrote:
> > I need a simple logic function, a two input AND feeding a two input OR
> > feeding another two input AND [see picture]. Since I don't need any
other
> > logic in the project I hate waste the space and use two chips, is
anyone
> > else's Boolean algebra less rusty that mine? Is there a one part
> > implementation (other than a PAL or CPLD)?
>
> What about a PIC? A 12F629 could do the same. TTYL
>

Sorry, I seem to have left out a crucial detail - 50MHz.

-Denny


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2004\10\14@172610 by Andrew Warren

flavicon
face
Denny Esterline <piclistspamKILLspammit.edu> wrote:

> I need a simple logic function, a two input AND feeding a two
> input OR feeding another two input AND [see picture]. Since I don't
> need any other logic in the project I hate waste the space and use
> two chips, is anyone else's Boolean algebra less rusty that mine?
> Is there a one part implementation (other than a PAL or CPLD)?

Danny:

A PIC could do it if you don't mind a six-microsecond propagation
delay...  

   ; Written for the 12C508A.
   ;
   ; GP0 = GND
   ; GP1 = A input
   ; GP2 = B input
   ; GP3 = C input
   ; GP4 = D input
   ; GP5 = OUTPUT
   ;
   ; OUTPUT = ((A and B) or C) and D

   LOOP:

       MOVF    GPIO,W
       ADDWF   PCL

       BCF     OUTPUT    ;0000 = 0
       GOTO    LOOP    
       BCF     OUTPUT    ;0001 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0010 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;0011 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;0100 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0101 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0110 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;0111 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;1000 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;1001 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;1010 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1011 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;1100 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1101 = 1
       GOTO    LOOP
       BCF     OUTPUT    ;1110 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1111 = 1
       GOTO    LOOP

       ; A second copy, since we don't know what GP5 will be
       ; when we execute the MOVF GPIO,W...

       BCF     OUTPUT    ;0000 = 0
       GOTO    LOOP    
       BCF     OUTPUT    ;0001 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0010 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;0011 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;0100 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0101 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;0110 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;0111 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;1000 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;1001 = 0
       GOTO    LOOP
       BCF     OUTPUT    ;1010 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1011 = 1
       GOTO    LOOP

       BCF     OUTPUT    ;1100 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1101 = 1
       GOTO    LOOP
       BCF     OUTPUT    ;1110 = 0
       GOTO    LOOP
       BSF     OUTPUT    ;1111 = 1
       GOTO    LOOP

-Andy  

=== Andrew Warren -- .....aiwKILLspamspam.....cypress.com
=== Principal Design Engineer
=== Cypress Semiconductor Corporation
===
=== Opinions expressed above do not
=== necessarily represent those of
=== Cypress Semiconductor Corporation

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2004\10\14@174435 by Jinx

face picon face
> umm. a PIC <vbg>

Like a 10F (>>>>> sampling now <<<<< nudge nudge)


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2004\10\14@174859 by Jinx

face picon face
> > What about a PIC? A 12F629 could do the same. TTYL
>
> Sorry, I seem to have left out a crucial detail - 50MHz.

OK, a PIC running on 100V and being threatened with a pointed
stick (dog-do optional)

An SX18 would do it, if you're geared up for Scenix that is

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2004\10\14@175324 by Marcel Duchamp

picon face
If, as you originally posted, your main criteria is "I hate waste the space
and use two chips", waste a little more and use 3 chips. SOT package
chips.  You can get single logic gates in SOT packages and I for one would
be very suprised if you can do the job in less space.  Of course, your
mileage may vary, etc.
MD

At 02:18 PM 10/14/04, you wrote:
{Quote hidden}

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2004\10\14@175721 by Denny Esterline

picon face
> If you inputs are A, B (going to the first AND) C (additional input to
the
> OR) and D (additional input to the last AND) then your diagram is:
>
> Out = ( A * B + C ) * D
>
> Using a 4 gate NAND chip, you can get
>
> Out = /( A * B + C ) * D
>
> In other words, the exact same thing, but with the output inverted or you
> can get
>
> Out = ( A * B + /C ) * D
>

There we go. The output was to feed a counter anyway, so an inverted output
really won't matter. Saves me a chip - I knew the piclist was good for
something other than consuming mass amounts of my time ;-)

-Denny


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DF(Y]*:8\9);)SIEH&J/FFF&Y"6><<LY)9YUVWHEGG@H4```[
`
end

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2004\10\14@181847 by Bob Ammerman

picon face
Try a 74xx151 multiplexer.

Naming the inputs from your original diagram:

A & B are the inputs to the left-side and gate.
C is the input to the or gate
D is the input to the right side and gate

Connect A, B and C to the A, B and C address inputs of the mux.

Connect D to mux inputs 3, 4, 5, 6 and 7

Connect the remaining mux inputs to ground.

The output will be the signal you want.

Bob Ammerman
RAm Systems




{Original Message removed}

2004\10\14@183406 by Denny Esterline

picon face
I had forgotten that trick. Would work fine, but James pointed me to a way
to get there with four NAND gates, which will work out for me.

Thanks though,
-Denny


{Quote hidden}

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2004\10\14@221403 by Dave Lag

picon face
two diodes and and resistor for the OR?
D
At 04:12 PM 10/14/04, you wrote:
>I need a simple logic function, a two input AND feeding a two input OR
>feeding another two input AND [see picture]. Since I don't need any other
>logic in the project I hate waste the space and use two chips, is anyone
>else's Boolean algebra less rusty that mine? Is there a one part
>implementation (other than a PAL or CPLD)?
>
>Thanks
>-Denny
>
>
>
>
>_______________________________________________
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>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

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2004\10\15@002323 by Anand Dhuru

flavicon
face
Hi,

Your second post about the 50MHz operation would probably rule this out, but
take a look at arblogic at http://www.eclectic-web.co.uk/mike/downloads.htm

One can burn virtually any boolean equation in a atandard EPROM.

Regards,

Anand


{Original Message removed}

2004\10\15@040948 by Morgan Olsson

flavicon
face
Dave Lag 04:15 2004-10-15:
>two diodes and and resistor for the OR?

That is wasting an R

A ->|---,
       o--- Q
B -[R]--´

____

Nice idea about the multiplexer, Bob!

/Morgan
--
Morgan Olsson, Kivik, Sweden


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2004\10\15@155934 by Peter L. Peres

picon face

On Fri, 15 Oct 2004, Anand Dhuru wrote:

> Hi,
>
> Your second post about the 50MHz operation would probably rule this out, but
> take a look at arblogic at http://www.eclectic-web.co.uk/mike/downloads.htm
>
> One can burn virtually any boolean equation in a atandard EPROM.

A 50MHz EPROM would be 10 nsec. Not an off the shelf part. You can do that
with a fast SRAM, but it must be loaded with data during boot. That works
but it takes more than one chip and burns a lot of power.

Peter
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2004\10\15@155945 by Peter L. Peres

picon face

On Thu, 14 Oct 2004, Denny Esterline wrote:

>> On Thu, 2004-10-14 at 16:12, Denny Esterline wrote:
>>> I need a simple logic function, a two input AND feeding a two input OR
>>> feeding another two input AND [see picture]. Since I don't need any
> other
>>> logic in the project I hate waste the space and use two chips, is
> anyone
>>> else's Boolean algebra less rusty that mine? Is there a one part
>>> implementation (other than a PAL or CPLD)?
>>
>> What about a PIC? A 12F629 could do the same. TTYL
>>
>
> Sorry, I seem to have left out a crucial detail - 50MHz.

Imho at 50MHz with that gate topology you are opening a can of worms
(glitches etc). Imho you should use a clocked flipflop or two to
re-register the output or there may be trouble, so there should be more
than 1 chip anyway. And the clocked flipflops have enables which you
could use creatively to implement your function.

Peter
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2004\10\15@155947 by Peter L. Peres

picon face

On Thu, 14 Oct 2004, Denny Esterline wrote:

> I had forgotten that trick. Would work fine, but James pointed me to a way
> to get there with four NAND gates, which will work out for me.

Just in case you're building a counter using a pic, my favorite
multiplexer is a resistor:


                           +----prescaler clk out (RA3)
                           |
in (low z) --R1(330Ohms)---*----counter input (RTCC for 16C54 ;-)

In my pic based counter (long time ago), I used a single section of 74HC00
wired as inverter, as buffer to drive the low z point. The counter was
tested to beyond 28MHz and would probably work to 50MHz. When RA3 is high
Z input pulses reach RTCC via R1. When RA3 is output it both forces the
RTCC input to the desired level (H or L) and can be used to clock out the
prescaler.

Peter
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2004\10\15@180859 by James Newtons Massmind

face picon face
I think I understand your suggestion, but doesn't the prescaler output cause
the counter to stop counting? Is that what you ment by "clock out the
prescaler"?

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> {Original Message removed}

2004\10\15@221614 by Bob Ammerman

picon face
From: "James Newtons Massmind" <jamesnewtonspamspam_OUTmassmind.org>
To: "'Microcontroller discussion list - Public.'" <@spam@piclistKILLspamspammit.edu>
Sent: Friday, October 15, 2004 6:08 PM
Subject: RE: [EE] AND-OR-AND - simplest implementation?


>I think I understand your suggestion, but doesn't the prescaler output
>cause
> the counter to stop counting? Is that what you ment by "clock out the
> prescaler"?
>
> ---
> James Newton: PICList webmaster/Admin

"Clocking out the prescaler" means providing enough additional input clocks
to the prescaler to cause the main counter to count once more. By counting
the number of such additional counts required you can determine what the
value of the prescaler was when you stopped the measurement, thus giving you
extra precision equal to the number of bits in the prescaler.

Bob Ammerman
RAm Systems

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2004\10\16@020909 by James Newtons Massmind

face picon face
Ok. It's only 11pm, I've read that paragraph 4 times now, and I still don't
got it.

When the prescaler output goes high, the external clocks can't be seen
anymore at the clock input and so it doesn't count any more. So the
prescaler output stays high... And we still aren't counting.

What am I missing?

---
James.



> {Original Message removed}

2004\10\16@084747 by Peter van Hoof

picon face
This is how it works:

-a pic output pin gates the counter input

-input pulses increment prescaler and at prescaler rollover the counter
increments

-time is up the gate pin is deactivated and the counter is switched over to
count pulses from a pic output pin

-by pulsing this pic output pin and checking after each pulse if the main
counter rolled over yet we can determine what the count in the prescaler was
thus recovering the full accuracy of the prescaler and counter combined

Peter

----- Original Message -----
From: "James Newtons Massmind" <KILLspamjamesnewtonKILLspamspammassmind.org>
To: "'Microcontroller discussion list - Public.'" <RemoveMEpiclistTakeThisOuTspammit.edu>
Sent: Saturday, October 16, 2004 2:08 AM
Subject: RE: [EE] AND-OR-AND - simplest implementation?


{Quote hidden}

>> {Original Message removed}

2004\10\16@091724 by Peter van Hoof

picon face
on this page http://www.piclist.com/techref/piclist/weedfreq.htm (yours) you
have the whole cirquit (and it is with all gates in ONE package) and has the
assembler listing

Peter

----- Original Message -----
From: "Peter van Hoof" <spamBeGonepvhspamBeGonespamadelphia.net>
To: "Microcontroller discussion list - Public." <TakeThisOuTpiclistEraseMEspamspam_OUTmit.edu>
Sent: Saturday, October 16, 2004 8:47 AM
Subject: Re: [EE] AND-OR-AND - simplest implementation?


{Quote hidden}

>>> {Original Message removed}

2004\10\16@143916 by Bob Ammerman

picon face
> Ok. It's only 11pm, I've read that paragraph 4 times now, and I still
> don't
> got it.
>
> When the prescaler output goes high, the external clocks can't be seen
> anymore at the clock input and so it doesn't count any more. So the
> prescaler output stays high... And we still aren't counting.
>
> What am I missing?

My understanding is that the original description was a bit confused. As I
see it the output pin gets tri-stated and the count accumultated. After the
appropriate interval the counter is stopped by driving the output pin hi.
Then the output is toggled as many times as needed to get the prescaler to
carry into the main counter.

Bob Ammerman
RAm Systems



>
>> {Original Message removed}

2004\10\16@152533 by Peter L. Peres

picon face

On Fri, 15 Oct 2004, James Newtons Massmind wrote:

> Ok. It's only 11pm, I've read that paragraph 4 times now, and I still don't
> got it.
>
> When the prescaler output goes high, the external clocks can't be seen
> anymore at the clock input and so it doesn't count any more. So the
> prescaler output stays high... And we still aren't counting.
>
> What am I missing?

See my other posting. The prescaler is in 'series' with rtcc. rtcc can be
read as a register but the prescaler can't. So you pulse it one pulse at a
time until rtcc increments by one. When it does, you have supplied k
pulses to it. If you count them in a decrementing counter, from 0, modulo
256, then when it increments the counter will contains th previous value
of rtcc (the value since before you started incrementing it).

Peter
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2004\10\16@152541 by Peter L. Peres

picon face

On Fri, 15 Oct 2004, James Newtons Massmind wrote:

> I think I understand your suggestion, but doesn't the prescaler output cause
> the counter to stop counting? Is that what you ment by "clock out the
> prescaler"?

The prescaler is 'welded' to the rtcc counter. So when the gate closes you
have the value in the counter and the value in the prescaler. The value in
the rtcc you read out using movf etc since it's a register. Then you have
the prescaler to deal with. The prescaler is 8 bits wide (in my case) and
takes up to 256 pulses to clear out. Meanwhile, you can't assign to rtcc
without clearing the prescaler. So this is done like:

       movf        RTCC,w                ; get current counter in w
       movwf        Frtcch                ; temp. rtcc storage, also output reg.
       clrf        Frtccl                ; it took zero pulses to increment rtcc

loop:
       movf        Frtcch,w        ; get stored value
       subwf        RTCC,w                ; compare: Z = 1 if not changed
       btfsc        STATUS,Z        ; not changed
       goto        done_ok                ; changed

       bsf        Fgate,Bgate        ; pulse rtcc once
       nop                        ; allow outputs to settle
       bcf        Fgate,Bgate        ; if rtcc overflows rtcc will increment

       decfsz        Frtccl,f        ; it took 1 more pulse to inc rtcc
       goto        loop                ; keep trying

done_ng:
       ; bad things happened. hardware fault. so do something about it

done_ok:
       ; Ftemp contains the value of rtcc since before we started

Peter

PS: this code is unchecked, and from memory. My counter actually uses 24
bits so clocking out involves an adjustment for the MSB carry which occurs
when/if rtcc,7 goes 1. My gate time is up to 100 seconds afair (with some
overflow at 50MHz - the point is to get it accurate for low frequency
like 32768Hz).
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2004\10\18@141707 by Paul VanGraafeiland

flavicon
face
Once upon a time Phil Eisermann said:
> > EraseMEpiclist-bouncesspammit.edu wrote:
> > I need a simple logic function, a two input AND feeding a two input OR
> > feeding another two input AND [see picture]. Since I don't need any
> > other logic in the project I hate waste the space and use two chips,
> > is anyone else's Boolean algebra less rusty that mine? Is there a one
> > part implementation (other than a PAL or CPLD)?
> >
>
> umm. a PIC <vbg>
>
> seriously, though. I don't see anything simpler than D[AB+C] e.g. the
> circuit you have shown. The only 'trick' i remember off the top of my
> head would be the old 'decoder as a minterm generator', but that was
> already old way back when I was young :) Do they still teach that in
> school? In any case it makes no sense in this application.
>
> Unless you can 'design-out' the need for the logic function?

When I first read this post I knew there was another way to do this, but I
couldn't remember what it was.  I was just sitting here thinking about
other things, and it came to me.  You need three 3-Input NAND gates, such
as found in a 74HC10 or equivalent.

Wire A, B and D as the inputs to the first NAND gate, giving !(ABD) as the
output.  Wire C and D to the second NAND gate, tying the third input high,
gives !(CD) as the output.  Lastly, you wire the outputs of the first two
NAND gates to inputs of the third, again tying the unused input high.  The
output from the third gate is now !( !(ABD)  !(CD) ).  Using DeMorgan's
theorem, this simplifies to ABD + CD, which is just another way of writing
D(AB+C).

I hope this is of some help.

Paul VanGraafeiland
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