Post by thread:[EE]:Logic Analyzer

> > We've just acquired ($20) a working Arium ML4400 Logic Analyzer with > > a 400 MHz 16 bit POD and manual I'm seriously looking at upgrading my [fairly] slow home-made 6800- based LA to a faster PIC-based one. What sampling technique is used for high speed capturing, eg 400MHz ? Is it the same method that digital scopes use ? The problem with using the direct save-to-RAM method is RAM speed. One way I thought of might be to have more than one RAM and cycle the samples to each RAM so as to meet the minimum write times of the more commonly available parts (35-70ns). Is this feasible or is there a more workable alternative ? Ideally I'd like to run the LA at 50MHz (20ns sampling) in order to capture the smallest pulses (or noise) in more modern uC circuits than the 6800 can cope with.

Jinx wrote: ..... >I'm seriously looking at upgrading my [fairly] slow home-made 6800- >based LA to a faster PIC-based one. What sampling technique is used >for high speed capturing, eg 400MHz ? Is it the same method that digital >scopes use ? The problem with using the direct save-to-RAM method is >RAM speed. One way I thought of might be to have more than one RAM >and cycle the samples to each RAM so as to meet the minimum write >times of the more commonly available parts (35-70ns). Bingo. I've seen general diagrams of some of the faster, >1 Ghz, sampling scopes - they use a row of "slower" [but still blistering] RAM chips, controlled by a tapped delay line of some sort - but at 400 Mhz speeds there are obviously serious issues with risetimes, propagation delay times/etc. Hardly a "$20" project. ================ Is this feasible >or is there a more workable alternative ? Ideally I'd like to run the LA at >50MHz (20ns sampling) in order to capture the smallest pulses (or noise) >in more modern uC circuits than the 6800 can cope with. > For 20 nsec, you can probably just do it with a single fast SRAM chip intended for cache memories. These go 5-7 nsec. And 74AC logic will probably handle this. Alternatively, you can probably do it with a single address counter, and an inverter [plus some muckaround] between the /CE lines on 2 SRAM chips, otherwise connected in parallel. [but then I'm not really a logic designer <:-))]. regards, - Dan Michaels ==============