Post by thread:[EE]: VHDL questions

Hi all, If there is anyone here who knows VHDL well and is willing to answer a few questions, please email me offlist (shb7 at cornell.edu). Most importantly, I'm interested in race conditions and the effects of routing delays on them and how to write VHDL to avoid them. Thanks, Sean

> If there is anyone here who knows VHDL well and is willing to answer a > few questions, please email me offlist (shb7 at cornell.edu). > I thought the whole point of mailing lists was that so people could benifit not just from the answers to thier own questions but from the answers of others too. > Most importantly, I'm interested in race conditions and the effects of > routing delays on them and how to write VHDL to avoid them. > The easiest way is to write your VHDL so everything happens on the edge of one clock then tell your synthisis tool the characteristics of that clock. Then the timing analyser in your synthisis tool should tell you whether timing requirements passed or not, if they don't pass then you either tweak the synthisis tool settings, reduce your clock speed, move to a higher speed grade of chip or introduce more registers in the signal path.