Post by thread:[EE]: VHDL Compiler

> Hello pic, > > Anyone can recomend me a good VHDL Compiler ? > Should I begin with VHDL or Verilog ? > Hearing advices... regards, Gus What devices will you be using, or do you just want to experiment? If so go to http://www.xilinx.com, they offer a free IDE that supports verilog and VHDL IIRC. It is pretty much the same tool as the one they sell for hundreds of dollars. TTYL -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

At 05:39 PM 15/10/2002 -0400, you wrote: > > Hello pic, > > > > Anyone can recomend me a good VHDL Compiler ? > > Should I begin with VHDL or Verilog ? > > Hearing advices... regards, Gus I've heard tell, though I'm not sure how accurate this is, that Verilog yields better results than VHDL. --Brendan -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

> At 05:39 PM 15/10/2002 -0400, you wrote: > > > Hello pic, > > > > > > Anyone can recomend me a good VHDL Compiler ? > > > Should I begin with VHDL or Verilog ? > > > Hearing advices... regards, Gus > > I've heard tell, though I'm not sure how accurate this is, that Verilog > yields better results than VHDL. I would think that Verilog might be more "forgiving" but I don't really think it could consistantly yield "better" results. TTYL -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

> > I've heard tell, though I'm not sure how accurate this is, that Verilog > > yields better results than VHDL. > > I would think that Verilog might be more "forgiving" but I don't > really >think it could consistantly yield "better" results. TTYL Personally, my only experience is with VHDL, and I have not tried Verilog Warp, made by Cypress, is the compiler I've used, but that doesn't do much for someone designing for Xilinx or aAmel, etc. The OP should decide what part he is designing for before looking at what compiler to use. I think that Xilinx has a fair number of free tools, though. I, personally, have very little opinion on which is better. (Verilog vs. VHDL) What I said, quoted above, comes from having read the results of a contest in '99. The overview can be found here: http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html?http://oldeee.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html The part I'm refering to is this: "reported that 8 out of the 9 Verilog designers managed to complete the conference's design contest yet *none* of the 5 VHDL designers could." However, he later stated "I'm going present *everything* that happened at the Design Contest, warts and all, and let *you* judge! At the end of court evidence, I'll ask you, the jury, to write an e-mail reply which I can publish in my column in the follow-up "Integrated System Design"" Before coming up with theories on how that could have happened, please do read the article from the link seen above. The conclusion that I drew from this is that the Verilog language may be slightly friendlier. That *does* lead to better results via less frustrated designers, who usually tend to think more clearly. --Brendan -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

> > I would think that Verilog might be more "forgiving" but I don't > > really > >think it could consistantly yield "better" results. TTYL > I, personally, have very little opinion on which is better. > (Verilog vs. VHDL) > > The conclusion that I drew from this is that the Verilog language may be > slightly friendlier. That *does* lead to better results via less > frustrated designers, who usually tend to think more clearly. Interesting link, personally I feel Verilog is more "natural" for a person coming from a computer programming background (which is most students these days). Verilog tends to "flow" more like a HLL then VHDL. With that said it also has the disadvantage of the user "forgetting" they are using a HDL and NOT a computer language which can lead to completely normal looking code that doesn't function (ask me how I know...). However, the same mistakes can be made with VHDL. FWIW I've been exposed to VHDL (at school) but have used Verilog exclusively (through my job) and although I perhaps should give VHDL another try I much prefer Verilog, at the moment. TTYL -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.