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'[EE]: Seperating grounds'
2001\04\01@154257 by Andy Jancura

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Hi,

>Some people think one of those gnds is for analog and the other is for
>digital, and should be used that way. However, I just measured several
>chips with my DMM, and got about 2 ohms between the gnd pins - which is
>actually same reading as between the 2 Vdd pins. So looks like they are
>simply tied together inside the chips. Personally, I always use a pcb
>trace between them.

Semiconductors have semi-conductance, what means, when you have two separate
conductors on one die, the die connect them together.

{Quote hidden}

Not exact on PIC. The GND pin on analog side is for analog part, not for
digital. Andy Kunz can you tell little bit more about this PIC speciality.
Or the MCU layout designer.

>I believe I read one post in there about using thinner ground traces for
>high
>frequency digital, so that it would cut down on the amount of frequency
>that
>gets back to the central connecting point.

>BAD idea.
>Ground fat, VCC thin.

What about fat Vcc, thin ground?

The efect is the same and sometimes the total impedance of power structure
is better.

Andrej

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2001\04\01@161957 by David VanHorn

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>
>What about fat Vcc, thin ground?
>
>The efect is the same and sometimes the total impedance of power structure
>is better.

Depends on where, but I don't like thin ground anywhere.

In my article, I describe my general approach to bypassing.
I want everything tied together with low impedance ground.
I want the bypass cap to return to the chip's GND pin as short as possible,
so I place the bypass at GND.
I use a fat track from VCC to bypass, to minimize impedance.
I use a thin track from the bypass to system VCC, maximizing impedance.
Finally, I flood GND, with some use of "no flood" zones or shoving traces
around, to keep sections isolated.

Ex: in an SMPS section, I would return all gnd pins to the gnd pin of an
SMPS chip, then a fat track from there to the system. Then in flooding, I
would make sure that only the fat track route actually gets out of that
section, but within the section, everything's flooded.  There are
exceptions even so, but the main idea is to follow the current, and make
sure it gets back to where it came from.



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2001\04\02@123349 by Bob

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Well, on the F876, F873, and F870, (28 pin devices, not 40 pin), there is only
one VDD, but two Vss's.  There is also an additional +Vref and -Vref, which
according to the data sheet ARE for the ADC (if you want them to be, or you can
use Vdd & Vss as your referrances).  Knowing that, I would "assume" that the
extra Vss is just there to allow that version of the PIC to sink more overall
current (more than it could source).





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2001\04\02@125958 by Dan Michaels

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Andy Jancura wrote:

>>Some people think one of those gnds is for analog and the other is for
>>digital, and should be used that way. However, I just measured several
>>chips with my DMM, and got about 2 ohms between the gnd pins - which is
>>actually same reading as between the 2 Vdd pins. So looks like they are
>>simply tied together inside the chips. Personally, I always use a pcb
>>trace between them.
>

>Semiconductors have semi-conductance, what means, when you have two separate
>conductors on one die, the die connect them together.
>

I do not understand this answer at all. Are you saying that the 2 ohms
I measure between the gnd pins is not an internal connection, but rather
a "sneak" path through the die? I don't think so. Going to other pins
you measure resistance in the Mohm range. I am sure there is a direct
internal connection between the gnd pins.

- dan michaels
http://www.oricomtech.com
=======================

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2001\04\02@151507 by Dan Michaels

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Dave Van Horn wrote:

The general idea is to let the bypass function as a "T" filter, so that
you're always using the PCB track impedances to steer HF currents where you
want them to go.

>In my article, I describe my general approach to bypassing.
>I want everything tied together with low impedance ground.
>I want the bypass cap to return to the chip's GND pin as short as possible,
>so I place the bypass at GND.
>I use a fat track from VCC to bypass, to minimize impedance.
>I use a thin track from the bypass to system VCC, maximizing impedance.


Dave, I can understand your considerations about thin [high impedance]
Vcc traces helping to trap high-frequency currents at the Vcc/local bypass
cap pointa, but I've always favored wide [low impedance] Vcc traces for
several reasons:

1 - bypass caps aren't perfect, so you'll still be running some noise
   currents back thru the Vcc traces. Since narrow traces have relatively
   high inductances compared to wide traces, I am afraid of ending up
   with nice radiative loops that transmit high frequency noise to
   the rest of the board. To my way of thinking, it is better to make
   the "total" impedance to gnd at the Vcc pin as low as possible,
   but ....... [?????????]

2 - using wide Vcc traces is a closer approximation than narrow traces
   to using a gnd plane, which everyone seems to agree is the ideal
   situation.

My gnd traces, of course, are always as wide as can be.

A note in passing - on pg 265 of Johnson's book, he says: "rule (2).
the impedance between power pins on any two gates should be just as
low as the impedance between ground pins". You can do this with heavy
gnd traces and bypass caps, but he notes the impedance of the caps
may not be low enough, and then he discusses using power planes along
with the gnd planes.

Isn't it wonderful this stuff is so much easier to understand than
slowing down to enter a lower "faster" earth orbit, that caused so
much consternation on pickle-ist lately, say what :).

best regards,
- dan michaels
http://www.oricomtech.com
===================

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2001\04\02@172308 by Herbert Graf

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> >>Some people think one of those gnds is for analog and the other is for
> >>digital, and should be used that way. However, I just measured several
> >>chips with my DMM, and got about 2 ohms between the gnd pins - which is
> >>actually same reading as between the 2 Vdd pins. So looks like they are
> >>simply tied together inside the chips. Personally, I always use a pcb
> >>trace between them.
> >
>
> >Semiconductors have semi-conductance, what means, when you have
> two separate
> >conductors on one die, the die connect them together.
> >
>
> I do not understand this answer at all. Are you saying that the 2 ohms
> I measure between the gnd pins is not an internal connection, but rather
> a "sneak" path through the die? I don't think so. Going to other pins
> you measure resistance in the Mohm range. I am sure there is a direct
> internal connection between the gnd pins.

       Those pins might be connected to two different places on the die and the
resistance you measure probably the resistance of the path from one pad to
the other. If the two wires were connected together you would read much less
than 2 ohms, at least I would think. TTYL

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