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PICList Thread
'[EE]: PAL Tools'
2000\06\07@201840 by Dan Michaels

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Anyone know of any cheapo tools, s.w. and h.w., for programming
PALs? The intent is to do only 1 or 2 chips, so I really would
prefer not having to spend $500 or $2000.

Main interest is doing chips with about 10 inputs and 8 "registered"
outputs. Anyone have favorite chips/vendors along this line?

best regards,
- Dan Michaels
Oricom Technologies
===================

2000\06\07@213646 by Bob Ammerman

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> Anyone know of any cheapo tools, s.w. and h.w., for programming
> PALs? The intent is to do only 1 or 2 chips, so I really would
> prefer not having to spend $500 or $2000.
>

Dan, let me guess - you're playing with the RAM counter replacement thing!
:-)

I'm very interested in where this thread goes myself. I would love to get
into PAL stuff relatively cheap. It would make a good adjunct to the PIC to
implement those high-speed functions that you can't manage in software.

Bob Ammerman
RAm Systems
(high performance, high function, low level software)

2000\06\07@225011 by Dan Larson

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On Wed, 7 Jun 2000 21:32:35 -0400, Bob Ammerman wrote:

>> Anyone know of any cheapo tools, s.w. and h.w., for programming
>> PALs? The intent is to do only 1 or 2 chips, so I really would
>> prefer not having to spend $500 or $2000.
>>
>
>Dan, let me guess - you're playing with the RAM counter replacement thing!
>:-)
>
>I'm very interested in where this thread goes myself. I would love to get
>into PAL stuff relatively cheap. It would make a good adjunct to the PIC to
>implement those high-speed functions that you can't manage in software.
>

I'd go with the Xinlinx CPLD's.  The starter kit with software, JTAG cable
and demo board is ~= $149.

The low-end XC9536 and XC9572 can be had in a 44-pin PLCC, which is easy to
prototype on perfboard because of the .10" spacing of the socket leads.  Those
parts have 36 and 72 macro cells respectively.  They are flash based and can be had
for $3 - $5 each from Digikey in onesies.  Other sizes are also available.

The schematic capture SW is nice, at least for a  non VHDL user....

See:

http://www.insight-electronics.com/xcellence/scalable/kit/cpld/index.html

Dan

2000\06\07@225539 by Dale Botkin

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On Wed, 7 Jun 2000, Bob Ammerman wrote:

> > Anyone know of any cheapo tools, s.w. and h.w., for programming
> > PALs? The intent is to do only 1 or 2 chips, so I really would
> > prefer not having to spend $500 or $2000.
> >
>
> Dan, let me guess - you're playing with the RAM counter replacement thing!
> :-)
>
> I'm very interested in where this thread goes myself. I would love to get
> into PAL stuff relatively cheap. It would make a good adjunct to the PIC to
> implement those high-speed functions that you can't manage in software.

::sigh::

I have an old JDR universal programmer that does PALs and GALS quite well,
along with EPROMS, 87xx MPUs, and a lot of other stuff.  I also have a few
Lattice GAL16V8A and maybe a 22V10 or two around.  Although I haven't used
this in a couple of years, I just can't let it go.  I paid WAY too much to
sell it for what I could get for it now, and I'm sure some day I'll REALLY
need it badly.  I would be happy to burn a few for you, though.  I also
have, somewhere, a copy of CUPL, which is a rudimentary but effective and
pretty easy to use tool for generating the hex files.

I have used PALs & GALs in a couple of products.  If you need speed and
flexibility and aren't concerned about power consumption, they're really
neat devices.  I like 'em.  Don't use 'em much any more, though.

Dale
---
The most exciting phrase to hear in science, the one that heralds new
discoveries, is not "Eureka!" (I found it!) but "That's funny ..."
               -- Isaac Asimov

2000\06\07@235541 by Dan Michaels
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Bob Ammerman wrote:
>> Anyone know of any cheapo tools, s.w. and h.w., for programming
>> PALs? The intent is to do only 1 or 2 chips, so I really would
>> prefer not having to spend $500 or $2000.
>>
>
>Dan, let me guess - you're playing with the RAM counter replacement thing!
>:-)
>

Yeah, seems all the discussion this past week about addressing SRAMs
rekindled my interest in trying to find a better route than using
4 74AC161 chips.

- Dan
=====

2000\06\08@011453 by Mark Willis

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Dan, I'll second Dale B's offer - Have a Needham's EMP-10 and EMP-20,
can burn those chips for you if you get the object files set up for the
burning.

Best if the parts fit the EMP-10 (Using the EMP-20 for another project a
lot right now, it's not at home always.)

If you buy the EMP-10 new it's $219.95 for the EMP-10, don't think I'd
call that "cheapo" though.  Don't have CUPL software where I can locate
it right now.  Most of the GAL/PAL stuff I've done, I could do manually
/ in my head, but not everyone likes to do that <G>  (Take a look, it's
not that bad.)

Dan L.:  Thanks - I needed that link.  Been meaning to get that, good
price.  Have you looked at Atmel's FPGA's?  I'd love to compare Xilynx's
to Atmel's parts.  Performance and cost...

 Mark

Dan Michaels wrote:
{Quote hidden}

--
I re-ship for small US & overseas businesses, world-wide.
(For private individuals at cost; ask.)

2000\06\08@012027 by William Chops Westfield

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If you're using PALs of any kind, you'll want to pay some attention to
the power consumption specs.  Even "low power" PALS tend to be rather
exhorbitant consumers compared to small microcontrollers (which is why
you see people using PICs and the like in places where PALs might have
been used.  A microcontroller makes a fine PAL if you're not worried about
speed...)

BillW

2000\06\08@045917 by Jan Lund

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Hi Dan.

> Anyone know of any cheapo tools, s.w. and h.w., for programming
> PALs?

Have you considered using ICT's PEEL's instead (Programmable Electrically
Eraseable Logic). They are pin and JEDEC compatible with the same size PALS.

I am not quite sure what a programmer costs (i bought mine 10 years ago),
but the design software is free.
Take a look at :

http://www.ictpld.com/

> Main interest is doing chips with about 10 inputs and 8 "registered"
> outputs. Anyone have favorite chips/vendors along this line?

That could be an 18CV8

Rgds

Jan

2000\06\08@061901 by Alan B. Pearce

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I got a program from my National Semiconductor distributor many years ago. They copied the
diskette while I waited, and gave it away for free. It assembles the JEDEC files from a
source file, and allowed me to do a couple of projects that required PALS. It would handle
all the bottom end devices up to the 22V10 family.

2000\06\08@112314 by Dan Michaels

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BillW wrote:
>If you're using PALs of any kind, you'll want to pay some attention to
>the power consumption specs.  Even "low power" PALS tend to be rather
>exhorbitant consumers compared to small microcontrollers (which is why
>you see people using PICs and the like in places where PALs might have
>been used.  A microcontroller makes a fine PAL if you're not worried about
>speed...)
>

I've done some prelim checking along this line. Seems there are
both bipolar and CMOS PALs available, and specs on the latter
indicate that power consumption varies with freq, like in other
CMOS devices. Numbers like 2 mA/Mhz. Also, the small version of the
CPLD that DanL. mentioned draws only 60-70 mA @ 50 Mhz.

Sounds lots better than the bipolar PALs and the 130 mA each for
2 'F style counters that I looked at.

- DanM

2000\06\08@114135 by Dan Michaels

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Dale Botkin wrote:
........
>I have an old JDR universal programmer that does PALs and GALS quite well,
>along with EPROMS, 87xx MPUs, and a lot of other stuff.  I also have a few
>Lattice GAL16V8A and maybe a 22V10 or two around.  Although I haven't used
>this in a couple of years, I just can't let it go.  I paid WAY too much to
>sell it for what I could get for it now, and I'm sure some day I'll REALLY
>need it badly.  I would be happy to burn a few for you, though.  I also
>have, somewhere, a copy of CUPL, which is a rudimentary but effective and
>pretty easy to use tool for generating the hex files.
.......


Dale, thanks for the "burn" offer. I'll footnote this email.

As it turns out I found a 1991 version of PLDshell/PLDasm from Intel
on my bookshelf, that I never looked at. It this of any use today?

Do you know if CUPL is available for download? Who the vendor is?

Thanks,
- Dan Michaels
==============

2000\06\08@114145 by Dan Michaels

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Dan Larson wrote:
......
>I'd go with the Xinlinx CPLD's.  The starter kit with software, JTAG cable
>and demo board is ~= $149.
>
>The low-end XC9536 and XC9572 can be had in a 44-pin PLCC, which is easy to
>prototype on perfboard because of the .10" spacing of the socket leads.  Those
>parts have 36 and 72 macro cells respectively.  They are flash based and
can be had
>for $3 - $5 each from Digikey in onesies.  Other sizes are also available.
.....

Thanks for the info, I downloaded the specsheet on the 9536 and it
looks like a possible. Relatively low current reqs. Price for parts
is good too, and one 44-pin PLCC might be preferable to using 2 24-pin
PAL chips.

thanks,
- Dan Michaels
==============

2000\06\08@114756 by smerchock, Steve

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Dan,

CUPL is made by Logical Devices ( http://www.logivaldevices.com ).
You can download the starter package for free. But it only
programs the 16V8. I bought the latest version of their
software for around $500.00. I haven't been able to play that
much with them unfortunately. Or you can look at the
Vantis/Lattice "MACH" starter package. You get the software,
44 pin PLCC programmer (ISP) and some other stuff for $49.00.


Best regards,
Steve



Steven Kosmerchock
Radio Frequency Systems
Phoenix  Az  USA
http://www.rfsworld.com

http://www.geocities.com/researchtriangle/lab/6584



{Original Message removed}

2000\06\08@121058 by Dan Michaels

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>Steven Kosmerchock wrote:
>Dan,
>
>CUPL is made by Logical Devices ( http://www.logivaldevices.com ).
>You can download the starter package for free. But it only
>programs the 16V8. I bought the latest version of their
>software for around $500.00. I haven't been able to play that
>much with them unfortunately. Or you can look at the
>Vantis/Lattice "MACH" starter package. You get the software,
>44 pin PLCC programmer (ISP) and some other stuff for $49.00.
>

Ah, $49 with programmer - this is more like what I had in
mind. Guess I have just spent $500 too darn many times to
"try" something out :-).

Thanks,
- Dan Michaels
==============

2000\06\08@122125 by Steve Landas

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I have the CUPL package I am using on some atf1508's. I went with cupl because we were on a tight schedule and I foolishly thought this was a mature product. The tools work but its one of the poorest windows implementations I have ever seen and there support is about a useful as speed brakes on a turtle. Atmel was very good at finding workarounds, without there support I'd never have finished the project. My advise is if theres something other than CUPL available, BUY IT.

2000\06\08@123346 by Dan Michaels

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Mark Willis wrote:
>Dan, I'll second Dale B's offer - Have a Needham's EMP-10 and EMP-20,
>can burn those chips for you if you get the object files set up for the
>burning.
>
>Best if the parts fit the EMP-10 (Using the EMP-20 for another project a
>lot right now, it's not at home always.)
>
>If you buy the EMP-10 new it's $219.95 for the EMP-10, don't think I'd
>call that "cheapo" though.  Don't have CUPL software where I can locate
>it right now.  Most of the GAL/PAL stuff I've done, I could do manually
>/ in my head, but not everyone likes to do that <G>  (Take a look, it's
>not that bad.)
........

Thanks for the info and the "burn" offer, Mark. Do you know if
CUPL is freely available somewhere, or has to be purchased?
And from whom?

best regards,
- Dan Michaels
Oricom Technologies
===================

2000\06\08@130313 by Dale Botkin

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On Thu, 8 Jun 2000, Dan Michaels wrote:

> As it turns out I found a 1991 version of PLDshell/PLDasm from Intel
> on my bookshelf, that I never looked at. It this of any use today?

I had that too...  near as I can recall, it's OK as long as you use Intel
part$.

> Do you know if CUPL is available for download? Who the vendor is?

I'm sure it's not, it's a commercial product.  My version was $100 from
JDR a few years ago (like 1990/91) and is a limited version that will only
do up to 22V10, I think.  It's been a while since I used any of it,
really.

Dale
---
The most exciting phrase to hear in science, the one that heralds new
discoveries, is not "Eureka!" (I found it!) but "That's funny ..."
               -- Isaac Asimov

2000\06\08@132610 by mike

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On Thu, 8 Jun 2000 09:41:58 -0600, you wrote:

>Mark Willis wrote:
>>Dan, I'll second Dale B's offer - Have a Needham's EMP-10 and EMP-20,
>>can burn those chips for you if you get the object files set up for the
>>burning.
>>
>>Best if the parts fit the EMP-10 (Using the EMP-20 for another project a
>>lot right now, it's not at home always.)
>>
>>If you buy the EMP-10 new it's $219.95 for the EMP-10, don't think I'd
>>call that "cheapo" though.  Don't have CUPL software where I can locate
>>it right now.  Most of the GAL/PAL stuff I've done, I could do manually
>>/ in my head, but not everyone likes to do that <G>  (Take a look, it's
>>not that bad.)
>........
>
>Thanks for the info and the "burn" offer, Mark. Do you know if
>CUPL is freely available somewhere, or has to be purchased?
>And from whom?
Atmel supply a version for their PLDs (which include some standard
architechtures like the 16V8) free - not sure if its on the web but I
think it's on their data CD.

2000\06\08@143034 by Dan Michaels

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Mike Harrison wrote:
.....
>Atmel supply a version for their PLDs (which include some standard
>architechtures like the 16V8) free - not sure if its on the web but I
>think it's on their data CD.
>

Thanks, Atmel has WinCUPL on their, good for 100 compiles
or 1 year, plus some ABEL stuff:

http://www.atmel.com/atmel/products/prod180.htm

best regards,
- Dan Michaels
==============

2000\06\08@143322 by Dan Michaels

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Steve Landas wrote:
>I have the CUPL package I am using on some atf1508's. I went with cupl
because we were on a tight schedule and I foolishly thought this was a
mature product. The tools work but its one of the poorest windows
implementations I have ever seen and there support is about a useful as
speed brakes on a turtle. Atmel was very good at finding workarounds,
without there support I'd never have finished the project. My advise is if
theres something other than CUPL available, BUY IT.
>
>

Hi Steve, as noted in another email, I found Atemel-WinCUPL on the
Atmel site, dated March 31, 2000 - maybe it has been improved since
you used it. They have some ABEL stuff there too.

Thanks,
- Dan Michaels
==============

2000\06\08@175434 by William Chops Westfield

face picon face
Out of curiosity, has anyone written tools to convert a PALASM like language
to PIC code?

BillW

2000\06\09@054946 by Peter L. Peres

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Hi,

which and how many medium size PALs replace a $0.6 [(CMOS)|(74C)]4040
address counter, do not require a programmer, and are second sourced ?

Peter

2000\06\09@060727 by Arthur Brown

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Use Gal's as they are reprogramable
seen a PPP for them published in electronic mag I think it was Elektor
Electronics 1993.

Regards Art

{Original Message removed}

2000\06\09@073327 by mike

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On Thu, 8 Jun 2000 14:52:05 PDT, you wrote:

>Out of curiosity, has anyone written tools to convert a PALASM like language
>to PIC code?
>
>BillW
One of Microchip's first app.notes when the 16c5x series came out was
on using it as a pld replacement - this might be of interest. Palasm
is a very low-level language so you might be able to write some macros
to achieve similar functionality.

2000\06\09@082400 by Steve Landas

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It's pretty tough to tell from the number of inputs and outputs which device
it will fit in to. It depends on what the pld is doing to these signals.
Small pld's like the 16v8 or 22v10 have a limited number of product terms and
have universal output enables, clocks, presets and clears. So even if you
only need 2 inputs and 2 registered outputs if they need individual clks' or
clears you might have to go to a bigger part. If your just doing
combinatorial logic a 22v10 will do just fine. Most mfgs make some pretty
inexpensive cpld's, such as Atmels 1500 series that allow multiple clocks,
individual preset and clears, and output enables.

Steve

2000\06\10@113536 by Byron A Jeff

face picon face
On Thu, Jun 08, 2000 at 09:19:21PM +0300, Peter L. Peres wrote:
> Hi,
>
> which and how many medium size PALs replace a $0.6 [(CMOS)|(74C)]4040
> address counter, do not require a programmer, and are second sourced ?

Actually that isn't a fair comparison. The real objective of the PAL/GAL is
to create a multibyte programmable counter. That way with a 13/14 bit interface
You can interface with up to 16 MB of RAM, with a 3 instruction sequential
cycle read time and up to 8 instruction or so random access time. With the 4040
while the sequential time isn't bad, there's simply no effective way to do
random access because it would require clearing the counter then clocking the
counter to the desired address.

Now let me describe this 13/14 bit interface. An 8 bit I/O port interfaces to
the data bus of the RAM and to the address select input. 2 additional bits
are used for the RAM chip select and R/W interface. Two additional bits
are used for latching and clocking the address interface. Finally an additional
1 to 2 bits can be used to select which address latch to write two. There are
two possible configs: a single clear bit which resets a counter to the lowest
address latch and subsequent latchings will count up higher address latches,
or 2 bits can be used to directly address the latch to be written.

Finally if space is really tight the R/W bit could be multiplexed to serve as
the clear bit for the address latches making a 12 bit interface.

So here's how you address the RAM:

1. Writing the address latch:
- RAM CS deactivated
- Use AL select to select the approprate latch (either by clearing to select
lowest latch or writing latch address to the 2 latch address bits.
- Write address for latch to 8 bit interface.
- Toggle latch write.
- Repeat for other latches.

2. Reading sequentially (address latches already set)
- Set R/W to read
- Activate CS
- Read byte from 8 bit data bus
- Toggle clock to advance to next address

* Note that if you want to sequential read a block that only the last two
instructions are required for subsequent bytes.

The bottom line is that such a chip (if low power) could be extremely useful.
Personally I think that such an interface could be done with a PIC16F877
using the PSP port. Essentially using a second PIC as the RAM address
interface. However I'm not sure if the speed of the interface would be
accptable though.

BAJ
>
> Peter

2000\06\10@122517 by Dan Michaels

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Byron A Jeff wrote:
>On Thu, Jun 08, 2000 at 09:19:21PM +0300, Peter L. Peres wrote:
>> Hi,
>>
>> which and how many medium size PALs replace a $0.6 [(CMOS)|(74C)]4040
>> address counter, do not require a programmer, and are second sourced ?
>

>Actually that isn't a fair comparison. The real objective of the PAL/GAL is
>to create a multibyte programmable counter. That way with a 13/14 bit interface
>You can interface with up to 16 MB of RAM, with a 3 instruction sequential
>cycle read time and up to 8 instruction or so random access time. With the 4040
>while the sequential time isn't bad, there's simply no effective way to do
>random access because it would require clearing the counter then clocking the
>counter to the desired address.
>

Yes, this was the point of my starting this thread. The '4040 provides
sequential addressing only, cannot be used for random access or for
addressing multiple data buffers, and can't provide anywhere near 20Mhz
accesses, since it is a ripple counter. With the 4 '161 counter approach
that I am wishing to streamline, all 16 counter bits change state
simultaneously.
=============

..........
>Personally I think that such an interface could be done with a PIC16F877
>using the PSP port. Essentially using a second PIC as the RAM address
>interface. However I'm not sure if the speed of the interface would be
>accptable though.
>

I am now developing another app where a single 16C74 takes care of 16
address and 8 data lines. It acts as a slave to another uC. The '74 has
just enough pins to do it all, inc a few for I/F to the host. My [very
rough] estimate is max read/write rate is only about 500Khz. I should
know more accurately in a few days.

regards,
- Dan Michaels
Oricom Technologies
http://www.sni.net/~oricom
==========================

2000\06\10@200155 by William Chops Westfield

face picon face
The relatively simple PALs and GALs, on the other hand, tend to be really
annoying in their lack of usable "flipflops."  Something like a 16R8 (or a
16V8) pretty much only has those 8 flipflops, and can't do anything more
than an 8bit counter.  Even in the more complex parts, flipflops tend to
be associated with I/O pins, do that it's difficult to impossible to do
something like a 32bit counter that it output on 8pins (one byte at a time.)
(This is a somewhat old and shallow impression - things MIGHT have changed.
I'm reminded of the times as a young electronics experimentor that I avoided
any project containing ICs.  I mean, if transistors cost $1 apiece, it was
OBVIOUS that I couldn't afford ICs, right?  Then I looked more closely at
at prices in the back of the magazine...)

The simplest PIC, by comparison, has MANY, MANY bits of "buried" registers.

BillW

2000\06\11@114330 by Tom Handley

picon face
  Dan, I've done some CPLD designs for interface to PICs. In your case the
following might be of use:

  This is an SRAM Address Generator and Chip Enable Controller intended for
use with PIC16Cxx processors using Port D for a data bus and Port E for
control. It supports standard memory devices up to 512K Bytes and provides 4
auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.

Hardware Interface
==================

  Inputs:

     D0..D7: 8-Bit Data Bus
     S0..S2: 3-Bit State Select (RAM address A0-7, A8-15, A16-18 and CEx)
        /CS: Chip-Enable. Active-Low

  Outputs:

     A0..A18: 19-Bit SRAM address or general purpose latch outputs
      /CSRAM: SRAM Chip Enable. Active-Low
        /CE1: Chip Enable 1. Active-Low
        /CE2: Chip Enable 2. Active-Low
        /CE3: Chip Enable 3. Active-Low
         CE4: Chip Enable 4. Active-High

     Note: CE4 is useful for generating an LCD module Enable (E) signal as
           well as a Latch-Enable (LE) for external latches.

  Typical PIC Interface:

     RA0..RA2:  S0..S2
     RD0..RD7:  D0..D7
          RE0: /RD. External Read Data
          RE1: /WR. External Write Data
          RE2: /CS

  You might want to consider Lattice Semiconductor. Lattice provides the
ispDesignExpert software with a free 6 month license which is easy to renew.
This is an incredibly powerful free software suite. While it lacks some
features of the commercial version such as VHDL entry, this level of
capability in a `starter package' is unprecedented in the industry. It
provides schematic and ABEL-HDL entry. Also included is a gate-level
functional and timing simulator with detailed timing analysis and a waveform
viewer. There are too many features to list here. The starter software
supports their ispLSI (up to 600 Macrocells), ispGAL, MACH (formerly
Vantis), GAL, and PAL devices.

  Programming the ISP (In-System-Programming) devices is trivial with just
a 5V supply. The Lattice software to do this is free and is included in the
ispDesignExpert package or as the separate ispDownload program. The buffered
ISP download cable uses a 74HC/LS367 and a few passives and connects to a PC
parallel port. Most folks already have the parts in their `stash'.

  To build the Lattice ispDownload cable, and see some simple designs that
have been tested with a PIC, see my web page at:

     http://www.teleport.com/~thandley/Wilbure.htm

  For more information about Lattice Semiconductor's products and to
download the ispDesignExpert or ispDownload software, see:

     http://www.latticesemi.com

  - Tom


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

2000\06\11@141326 by Dan Michaels

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Tom Handley wrote:
>   Dan, I've done some CPLD designs for interface to PICs. In your case the
>following might be of use:
>
>   This is an SRAM Address Generator and Chip Enable Controller intended for
>use with PIC16Cxx processors using Port D for a data bus and Port E for
>control. It supports standard memory devices up to 512K Bytes and provides 4
>auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
>ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.
>

Hi Tom, sounds like you've been there, done that already.
Can you answer:

- do you sell these chips preprogrammed?
- max count rate of your sol'n?
- chip current draw?
- cost of basic blank chip?

Thanks,
- Dan Michaels
==============

2000\06\11@171227 by Peter L. Peres

picon face
Hi,

thank you for the explanations. Wrt '161 based address counters. I'd like
to remind the complete sequence PRNG with minimal feedback as address
counter. Due to the way it works it can go to 1/(2*Tprop) clock and I have
used 74A(S?)273 (I think) with clock at 66 MHz and room to spare. This is
even loadable if a hack is used (resistors to connect the stages and
tristate buffer forcing over them to load). A 16 bit counter uses 2 x 273
and 1 XOR gate + 1 inverter if I'm not wrong. There is a reset problem but
the 273 has a reset input so it's ok. I also used a 273 as a state counter
in the same project. Propagating a bit through it with all the cells
connected in series ;-). There is a neat VHDL implementation along these
lines (address counter) FYI, and there is a table of feedback points in an
appnote from Lattice or Altera I think. Of course the VHDL version is
loadable.

Peter

2000\06\12@162851 by jamesnewton

face picon face
Tom, how much do you want for preprogrammed copies of that chip?

---
James Newton spam_OUTjamesnewtonTakeThisOuTspamgeocities.com 1-619-652-0593


{Original Message removed}

2000\06\13@044424 by TOM THERON

flavicon
face
Subject: [EE]: PAL Tools


>Anyone know of any cheapo tools, s.w. and h.w., for programming
>PALs? The intent is to do only 1 or 2 chips, so I really would
>prefer not having to spend $500 or $2000.

I use Altera 7032 quite a lot, maybe a little bit of overkill for you. Their
design tools are for free (check out http://www.altera.com). Only problem is
getting the fuse map into the chip. They do have ISP capability, but you
need a converter that will convert data from parallel port  to the chip
format. Altera's converter is VERY expensive, but you might find al cheapo
3d vendor converters if you ask around. btw, they call it a ByteBlaster, and
it converts to serial JTAG format. The data download process is supported in
their development software.

I also use GAL16V8/20V8/22V10 - more likely what you need. I use Logic Lite,
(kinda very basic, but I got it for free) to do the coding, and have an
EXPRO 80 (not available in the market any more) for programming the chips.

I know Lattice also features ISP, and free sw tools, I guess. Don't know
about program loading/converting. I haven't checked them out lately, simply
because I use Altera most of the time.

Rgds
Tom

.....mmsesysKILLspamspam@spam@icon.co.za

===================

2000\06\13@160149 by Tom Handley

picon face
At 12:12 PM 6/11/00 -0600, Dan Michaels wrote:
>Hi Tom, sounds like you've been there, done that already.
>Can you answer:
>
>- do you sell these chips preprogrammed?
>- max count rate of your sol'n?
>- chip current draw?
>- cost of basic blank chip?

  Dan, I'm not setup to provide preprogrammed chips. If did a few it would
be too expensive. Programming them is easy with the free software using the
simple buffered download cable on my web site.

  This particular design doesn't use a counter though I have a serial
version. The basic specs are:

DC Electrical Characteristics (+5Vcc, 25C)
==============================================================

VOL   Output Low Voltage ..................  0.4V Max
VOH   Output High Voltage .................  2.4V Min
IOL   Output Sink Current .................  8ma
IOH   Output Source Current ............... -4ma
IIL   Input or I/O Low Leakage Current .... -10ua Max
IIH   Input or I/O High Leakage Current ...  10ua Max
Ipu   I/O Active Pull-up Current .......... -150ua Max
Icc   Supply Current (-80) ................  48ma Typ. 76ma Max
Icc   Supply Current (-100) ...............  48ma Typ. 84ma Max
Icc   Supply Current (-125) ...............  48ma Typ. 91ma Max
* I/O Pin Capacitance is typically 8pf at 1MHz and 25C.
* See Lattice Semiconductor Data Book for Full Specifications!


Timing Characteristics (-80, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 42.9ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 30.9ns Max
Tda    Data Bus to Address Tpd ............. 18.4ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 43.1ns Max

Timing Characteristics (-100, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 33.0ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 24.1ns Max
Tda    Data Bus to Address Tpd ............. 12.9ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 33.2ns Max

Timing Characteristics (-125, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 25.2ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 18.9ns Max
Tda    Data Bus to Address Tpd ............. 10.0ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 25.2ns Max

  As far as pricing, I just took a look at Arrow and Avnet and `gawd' I was
shocked... The ispLSI1016E-100LJ use to be around $6 in singles. Avnet's
pricing from 25-99/100+ is:

     -125LJ = 10.73/8.53
     -100LJ =  6.33/4.95
     - 80LJ =     ?/3.85

  It's even worse at Arrow... In any quantity the prices are:

     -125LJ = 14.01
     -100LJ =  8.93

  - Tom

{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

2000\06\13@210336 by Dan Michaels

flavicon
face
Tom Handley wrote:
>At 12:12 PM 6/11/00 -0600, Dan Michaels wrote:
>>Hi Tom, sounds like you've been there, done that already.
>>Can you answer:
>>
>>- do you sell these chips preprogrammed?
>>- max count rate of your sol'n?
>>- chip current draw?
>>- cost of basic blank chip?
>
>   Dan, I'm not setup to provide preprogrammed chips. If did a few it would
>be too expensive. Programming them is easy with the free software using the
>simple buffered download cable on my web site.
.......


Hi, Tom, thanks for the great info on Lattice. I was really only
after what I thought would come off the top of your head, but the
more the better. From looking at your site, I thought you might
actually be shipping these guys.

Given the Lattice prices/etc, it looks like the Xilinx XC9536
that Dan Larson mentioned, at $3.30/qty 1 Digikey, might be a
good contender for my project.
===========

>   It's even worse at Arrow... In any quantity the prices are:
>
>      -125LJ = 14.01
>      -100LJ =  8.93

Whew. And interesting you should mention Arrow. I just received an
order of PICs from them yesterday - their prices seem to be much
higher than last year - almost as bad as Digikey now - and they
didn't even have 4 of the 6 different parts I was after. They are
certainly not the guys to order small quantities from.

Thanks for the info,
- Dan Michaels
==============

2000\06\16@035452 by Tom Handley

picon face
At 12:12 PM 6/11/00 -0600, Dan Michaels wrote:
>Hi Tom, sounds like you've been there, done that already.
>Can you answer:
>
>- do you sell these chips preprogrammed?
>- max count rate of your sol'n?
>- chip current draw?
>- cost of basic blank chip?

  Dan, I'm not setup to provide preprogrammed chips. If did a few it would
be too expensive. Programming them is easy with the free software using the
simple buffered download cable on my web site.

  This particular design doesn't use a counter though I have a serial
version. The basic specs are:

DC Electrical Characteristics (+5Vcc, 25C)
==============================================================

VOL   Output Low Voltage ..................  0.4V Max
VOH   Output High Voltage .................  2.4V Min
IOL   Output Sink Current .................  8ma
IOH   Output Source Current ............... -4ma
IIL   Input or I/O Low Leakage Current .... -10ua Max
IIH   Input or I/O High Leakage Current ...  10ua Max
Ipu   I/O Active Pull-up Current .......... -150ua Max
Icc   Supply Current (-80) ................  48ma Typ. 76ma Max
Icc   Supply Current (-100) ...............  48ma Typ. 84ma Max
Icc   Supply Current (-125) ...............  48ma Typ. 91ma Max
* I/O Pin Capacitance is typically 8pf at 1MHz and 25C.
* See Lattice Semiconductor Data Book for Full Specifications!


Timing Characteristics (-80, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 42.9ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 30.9ns Max
Tda    Data Bus to Address Tpd ............. 18.4ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 43.1ns Max

Timing Characteristics (-100, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 33.0ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 24.1ns Max
Tda    Data Bus to Address Tpd ............. 12.9ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 33.2ns Max

Timing Characteristics (-125, +5Vcc, 25C)
==============================================================
Tcsa   /CS to Address Tpd .................. 25.2ns Max
Tcsc   /CS to CE1,CE2,CE3,CE4,CSRAM Tpd .... 18.9ns Max
Tda    Data Bus to Address Tpd ............. 10.0ns Max
Tsx    S0,S1,S2 State Select Tpd ........... 25.2ns Max

  As far as pricing, I just took a look at Arrow and Avnet and `gawd' I was
shocked... The ispLSI1016E-100LJ use to be around $6 in singles. Avnet's
pricing from 25-99/100+ is:

     -125LJ = 10.73/8.53
     -100LJ =  6.33/4.95
     - 80LJ =     ?/3.85

  It's even worse at Arrow... In any quantity the prices are:

     -125LJ = 14.01
     -100LJ =  8.93

  - Tom

{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

2000\06\16@103422 by Tom Handley

picon face
  Dan, I've done some CPLD designs for interface to PICs. In your case the
following might be of use:

  This is an SRAM Address Generator and Chip Enable Controller intended for
use with PIC16Cxx processors using Port D for a data bus and Port E for
control. It supports standard memory devices up to 512K Bytes and provides 4
auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.

Hardware Interface
==================

  Inputs:

     D0..D7: 8-Bit Data Bus
     S0..S2: 3-Bit State Select (RAM address A0-7, A8-15, A16-18 and CEx)
        /CS: Chip-Enable. Active-Low

  Outputs:

     A0..A18: 19-Bit SRAM address or general purpose latch outputs
      /CSRAM: SRAM Chip Enable. Active-Low
        /CE1: Chip Enable 1. Active-Low
        /CE2: Chip Enable 2. Active-Low
        /CE3: Chip Enable 3. Active-Low
         CE4: Chip Enable 4. Active-High

     Note: CE4 is useful for generating an LCD module Enable (E) signal as
           well as a Latch-Enable (LE) for external latches.

  Typical PIC Interface:

     RA0..RA2:  S0..S2
     RD0..RD7:  D0..D7
          RE0: /RD. External Read Data
          RE1: /WR. External Write Data
          RE2: /CS

  You might want to consider Lattice Semiconductor. Lattice provides the
ispDesignExpert software with a free 6 month license which is easy to renew.
This is an incredibly powerful free software suite. While it lacks some
features of the commercial version such as VHDL entry, this level of
capability in a `starter package' is unprecedented in the industry. It
provides schematic and ABEL-HDL entry. Also included is a gate-level
functional and timing simulator with detailed timing analysis and a waveform
viewer. There are too many features to list here. The starter software
supports their ispLSI (up to 600 Macrocells), ispGAL, MACH (formerly
Vantis), GAL, and PAL devices.

  Programming the ISP (In-System-Programming) devices is trivial with just
a 5V supply. The Lattice software to do this is free and is included in the
ispDesignExpert package or as the separate ispDownload program. The buffered
ISP download cable uses a 74HC/LS367 and a few passives and connects to a PC
parallel port. Most folks already have the parts in their `stash'.

  To build the Lattice ispDownload cable, and see some simple designs that
have been tested with a PIC, see my web page at:

     http://www.teleport.com/~thandley/Wilbure.htm

  For more information about Lattice Semiconductor's products and to
download the ispDesignExpert or ispDownload software, see:

     http://www.latticesemi.com

  - Tom


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

2000\06\16@105828 by Dan Michaels

flavicon
face
Tom Handley wrote:
>   Dan, I've done some CPLD designs for interface to PICs. In your case the
>following might be of use:
>
>   This is an SRAM Address Generator and Chip Enable Controller intended for
>use with PIC16Cxx processors using Port D for a data bus and Port E for
>control. It supports standard memory devices up to 512K Bytes and provides 4
>auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
>ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.
>

Hi Tom, sounds like you've been there, done that already.
Can you answer:

- do you sell these chips preprogrammed?
- max count rate of your sol'n?
- chip current draw?
- cost of basic blank chip?

Thanks,
- Dan Michaels
==============

2000\06\16@111908 by Peter L. Peres

picon face
Hi,

thank you for the explanations. Wrt '161 based address counters. I'd like
to remind the complete sequence PRNG with minimal feedback as address
counter. Due to the way it works it can go to 1/(2*Tprop) clock and I have
used 74A(S?)273 (I think) with clock at 66 MHz and room to spare. This is
even loadable if a hack is used (resistors to connect the stages and
tristate buffer forcing over them to load). A 16 bit counter uses 2 x 273
and 1 XOR gate + 1 inverter if I'm not wrong. There is a reset problem but
the 273 has a reset input so it's ok. I also used a 273 as a state counter
in the same project. Propagating a bit through it with all the cells
connected in series ;-). There is a neat VHDL implementation along these
lines (address counter) FYI, and there is a table of feedback points in an
appnote from Lattice or Altera I think. Of course the VHDL version is
loadable.

Peter

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