Post by thread:[EE]: N channel MOSFET

I am planning on doing some experiments with DC to DC converters, switching power supplies, particularly for battery use. As part of this I was looking for a few power FETs that might be generally useful and cheap enough to keep a bunch in stock for whatever might come up on short notice. I spent some quality time on manufacturer's and reseller's web pages to find a few good tradeoffs. In short, I was impressed with what is now available in N channel MOSFETs. In particular the IRFU3706 looks like a great little device. At 10V gate drive, it has 9mOms resistance, but is also speced to 11mOhms at 4.5V and 23mOhms at 2.8V. At these ratings it can be directly controlled from a battery operated LF PIC and still essentially act like a dead short when turned on. The device can handle up to 75A within the dissipation requirements. It comes in an "I-Pak" package, which is sorta like a TO-220. The IRFR3706 is the same device in a surface mount package which would be more suitable for production but maybe less desirable for hobbyist or quick experimenting. About the only significant "limitation" of this device is that it only goes to 20Vdss, which should be fine however for the vast majority of battery operated projects. The other good news is that this device is surprisingly cheap, only $.65 in singles or $.57 each for 100 from Richardson Electronics. I just bought 100 of them for $68.80 including tax and shipping. Now if things only looked this good for P channel MOSFETS... ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

> You should take a look at the IRF5305 P-channel. Not so impressive as > the N channel but still cheap and good enough for most application. 30A, > 55V, 0.06 ohms RDS on. It is preety robust, I have been using it for a while > and even "hard" shorts with a car battery and just 0.1 ohms series resistor > usually blows up the resistor instead of the FET ! Yes, I keep a few of those around to. I used this FET as the switching element in the buck converter of my battery charger. Unfortunately this FET is only speced for 10V gate drive, which makes it unsuitable for direct connection to a PIC or many battery applications where nothing exceeds 6V or 3V. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

Olin Lathrop wrote: > > I am planning on doing some experiments with DC to DC converters, switching > power supplies, particularly for battery use. > In particular the IRFU3706 looks like a great little device. > The device can handle up to 75A within the dissipation requirements. It > comes in an "I-Pak" package, which is sorta like a TO-220. The IRFR3706 is > About the only significant "limitation" of this device is that it only goes > to 20Vdss, which should be fine however for the vast majority of battery Remember to use a decent (hefty?) RC series "snubber" across the thing, i've seen a lot of failures with low volt D-S fets. Not hard to get tiny spikes >20v, with nasty results. The spikes don't need to have much energy to soon cause failure either. :o) -Roman -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

Roman, I've heard people talk about "snubbers". Can you tell me what they do and give an example of one for on an N channel MOSFET controlling fairly high current (10A+)? Thanks, Gary At 06:11 AM 7/3/2002 +1000, Roman Black wrote: {Quote hidden}>Olin Lathrop wrote: > > > > I am planning on doing some experiments with DC to DC converters, switching > > power supplies, particularly for battery use. > > > In particular the IRFU3706 looks like a great little device. > > > The device can handle up to 75A within the dissipation requirements. It > > comes in an "I-Pak" package, which is sorta like a TO-220. The IRFR3706 is > > About the only significant "limitation" of this device is that it only goes > > to 20Vdss, which should be fine however for the vast majority of battery > > >Remember to use a decent (hefty?) RC series "snubber" >across the thing, i've seen a lot of failures with low >volt D-S fets. Not hard to get tiny spikes >20v, with >nasty results. The spikes don't need to have much energy >to soon cause failure either. :o) >-Roman > >-- >http://www.piclist.com hint: The list server can filter out subtopics >(like ads or off topics) for you. See http://www.piclist.com/#topics Gary Neal Research Assistant - Drivetrain Technology Center Applied Research Laboratory - Penn State University PO Box 30 Research Building West North Atherton Street State College, PA 16801 814-863-5468 (phone) 814-863-6185 (fax) -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

Hi Gary, usually they are a R and C in series, placed across circuit components that may be voltage critical. These absorb spike energy and dissipate it as heat on the R. Common values across a 10A mosfet may be 10 ohms R + 0.022uF C. Best system is to tune the thing on the CRO, use as much snubbing as you can before you slow down the turn on/off of the FET and it starts to waste heat. I can offer suggestions for your 10A circuit if you email me a copy. -Roman Gary Neal wrote: {Quote hidden}> > Roman, > > I've heard people talk about "snubbers". Can you tell me what > they do and give an example of one for on an N channel MOSFET controlling > fairly high current (10A+)? > > Thanks, > > Gary > > At 06:11 AM 7/3/2002 +1000, Roman Black wrote: > >Olin Lathrop wrote: > > > > > > I am planning on doing some experiments with DC to DC converters, switching > > > power supplies, particularly for battery use. > > > > > In particular the IRFU3706 looks like a great little device. > > > > > The device can handle up to 75A within the dissipation requirements. It > > > comes in an "I-Pak" package, which is sorta like a TO-220. The IRFR3706 is > > > About the only significant "limitation" of this device is that it only goes > > > to 20Vdss, which should be fine however for the vast majority of battery > > > > > >Remember to use a decent (hefty?) RC series "snubber" > >across the thing, i've seen a lot of failures with low > >volt D-S fets. Not hard to get tiny spikes >20v, with > >nasty results. The spikes don't need to have much energy > >to soon cause failure either. :o) > >-Roman > > > >-- > >http://www.piclist.com hint: The list server can filter out subtopics > >(like ads or off topics) for you. See http://www.piclist.com/#topics > > Gary Neal > Research Assistant - Drivetrain Technology Center > Applied Research Laboratory - Penn State University > PO Box 30 > Research Building West > North Atherton Street > State College, PA 16801 > 814-863-5468 (phone) > 814-863-6185 (fax) > > -- > http://www.piclist.com hint: The PICList is archived three different > ways. See http://www.piclist.com/#archives for details. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

>I've heard people talk about "snubbers". Can you >tell me what they do and give an example of one >for on an N channel MOSFET controlling fairly >high current (10A+)? Well I know I am not Roman, but.. on many circuits where inductive loads are switched there will typically be a network consisting of a resistor and capacitor in series, across either the driving transistor or the load. This is the snubber network. It may be a diode (as put across a relay coil) in the simplest form. To determine the values of these components is very circuit dependant. Things that come into consideration are maximum dV/dT for the device being protected, the value of inductance producing the spike, and the maximum voltage allowed across anything. Do also remember that fitting such a network will also have an effect on the turn on current through the device you seek to protect. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

Roman Black wrote: > Remember to use a decent (hefty?) RC series "snubber" > across the thing, i've seen a lot of failures with low > volt D-S fets. Not hard to get tiny spikes >20v, with > nasty results. The spikes don't need to have much energy > to soon cause failure either. :o) Considering the large GS capacitance, I'd guess most circuits would form an integrator. (Tiny spikes make NO difference, nor do they puncture the gate.) My experience in LARGE FETs is the failure mode is the large dI/dT, I can tell you about blowing SEVERAL 200 amp FETs by grounding the gate! > > -Roman > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics -- * | __O Thomas C. Sefranek spam_OUTtcsTakeThisOuTcmcorp.com |_-\<,_ Amateur Radio Operator: WA1RHP (*)/ (*) Bicycle mobile on 145.41, 448.625 MHz hamradio.cmcorp.com/inventory/Inventory.html http://www.harvardrepeater.org -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

On Sun, 7 Jul 2002, Thomas C. Sefranek wrote: >Roman Black wrote: > >> Remember to use a decent (hefty?) RC series "snubber" >> across the thing, i've seen a lot of failures with low >> volt D-S fets. Not hard to get tiny spikes >20v, with >> nasty results. The spikes don't need to have much energy >> to soon cause failure either. :o) > >Considering the large GS capacitance, I'd guess most circuits would form an >integrator. GS capacitance ~= GD capacitance on many MOSFETs. If you do not control the gate firmly in both directions then you are likely going to have surprises. If you scope the gate on a switching FET you can see the changeover points very clearly. Not only is Cgd large but it changes with the applied D voltage. >(Tiny spikes make NO difference, nor do they puncture the gate.) My experience with tiny spikes is, that they can breakdown the gates just fine, at least on FETs <= 100A, or cause invisible failures that doom the device later. Maybe yours have integral gate protection diodes. >My experience in LARGE FETs is the failure mode is the large dI/dT, >I can tell you about blowing SEVERAL 200 amp FETs by grounding the gate! Afaik you can blow the FETs by grounding the gate and then applying a large dU/dt on the drain. The coupling capacitance between D and G will produce enough voltage on the gate to breakdown the oxide (the inductance etc from the gate to the driver is enough for this). Is this what you mean ? Many mains SMPSUs with FETs fail this way or so it seems. FETs with integral zeners on the gates are much tougher. The only dI/dt failures I know of involve lead inductance and/or other inductors in the circuit. Afaik one of the reasons for using FETs is the very high switching speed achievable. Peter -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

On 8 Jul 2002 at 0:36, Peter L. Peres wrote: > On Sun, 7 Jul 2002, Thomas C. Sefranek wrote: > >Considering the large GS capacitance, I'd guess most circuits would form an > >integrator. > > GS capacitance ~= GD capacitance on many MOSFETs. If you do not control > the gate firmly in both directions then you are likely going to have > surprises. If you scope the gate on a switching FET you can see the > changeover points very clearly. Not only is Cgd large but it changes with > the applied D voltage. I do see the miller effects on the gate voltage. > > >(Tiny spikes make NO difference, nor do they puncture the gate.) > > My experience with tiny spikes is, that they can breakdown the gates just > fine, at least on FETs <= 100A, or cause invisible failures that doom the > device later. Maybe yours have integral gate protection diodes. Since I = C(dV/dT), you need a HEAVY current as the "spike" gets tiny. I grabbed the MTM45N05E spec. as an example. For a 100 nS pulse and 20 volts you need to supply .9 AMP! (10 nS and you need 9 AMPS! and that's for only 20 volts!) So, your spike driver has to have real good current ability, AND you must not have included the gate ballast resistor. > > >My experience in LARGE FETs is the failure mode is the large dI/dT, > >I can tell you about blowing SEVERAL 200 amp FETs by grounding the gate! > > Afaik you can blow the FETs by grounding the gate and then applying a > large dU/dt on the drain. If I shut off the gate there MUST be a large change in drian voltage. Well, large is relative, but at least the applied voltage. Assuming the integral diode can clamp the inductive effects.... The coupling capacitance between D and G will > produce enough voltage on the gate to breakdown the oxide (the inductance > etc from the gate to the driver is enough for this). Is this what you mean > ? If the gate is well grounded, and the souce is well grounded, how do I get gate voltage? (If I had an inductive gate ground I can see it happening...) I have a demo with a 100 amp source of 12 volts to the drain. (MTM200N06) was the FET. I have a load in the drain to supply to show the current. 1K2 watts. The Source is well grounded, the FET well Heat-sinked. I have an external 15 volt zener from gate to source. I apply 10 volt charge to the gate, all is well, 100 amps flow. (Disconecting the gate charge source to show the charge remains on the gate...) I apply a 1/2 inch piece of wire between the gate as source terminals to short the gate charge... The FET fails! Gate to source short! Motorola said it's the gate bonding wire which is inductiveenough to cause this. (They also had a substrate explaination....) {Quote hidden}>Many mains SMPSUs with FETs fail this way or so it seems. FETs with > integral zeners on the gates are much tougher. The only dI/dt failures I > know of involve lead inductance and/or other inductors in the circuit. > Afaik one of the reasons for using FETs is the very high switching speed > achievable. > > Peter > > -- > http://www.piclist.com hint: The PICList is archived three different > ways. See http://www.piclist.com/#archives for details. > > * | __O Thomas C. Sefranek .....tcsKILLspam@spam@cmcorp.com |_-\<,_ Amateur Radio Operator: WA1RHP (*)/ (*) Bicycle mobile on 145.41, 448.625 MHz ARRL Instructor, Technical Specialist, VE Contact. hamradio.cmcorp.com/inventory/Inventory.html http://www.harvardrepeater.org -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

On Mon, 8 Jul 2002, Thomas C. Sefranek wrote: {Quote hidden}>On 8 Jul 2002 at 0:36, Peter L. Peres wrote: > >> On Sun, 7 Jul 2002, Thomas C. Sefranek wrote: > >> >Considering the large GS capacitance, I'd guess most circuits would form an >> >integrator. >> >> GS capacitance ~= GD capacitance on many MOSFETs. If you do not control >> the gate firmly in both directions then you are likely going to have >> surprises. If you scope the gate on a switching FET you can see the >> changeover points very clearly. Not only is Cgd large but it changes with >> the applied D voltage. > >I do see the miller effects on the gate voltage. >> >> >(Tiny spikes make NO difference, nor do they puncture the gate.) >> >> My experience with tiny spikes is, that they can breakdown the gates just >> fine, at least on FETs <= 100A, or cause invisible failures that doom the >> device later. Maybe yours have integral gate protection diodes. > >Since I = C(dV/dT), you need a HEAVY current as the "spike" gets tiny. >I grabbed the MTM45N05E spec. as an example. >For a 100 nS pulse and 20 volts you need to supply .9 AMP! >(10 nS and you need 9 AMPS! and that's for only 20 volts!) >So, your spike driver has to have real good current ability, >AND you must not have included the gate ballast resistor. Your reasoning is good and I aggree with it but still FETs do not like spikes on the gate. Perhaps there is a transmission line issue inside the gate structure. After all, C is distributed in the device. This means that a high voltage spike will cause high voltage at least across a small part of the oxide before it has time to propagate. I guesstimate that at 10nsec a 100A device will have most of the voltage applied near the gate bonding wire for the first few ns at least. The required current for causing breakdown should be related to the impedance of the transmission line formed inside the device between G and S in that mode, and it would probably be a fraction of what you calculated. There must be a solid reason for virtually all CMOS chip manufacturers to waste space for clamping diodes on their dies after all. >> >My experience in LARGE FETs is the failure mode is the large dI/dT, >> >I can tell you about blowing SEVERAL 200 amp FETs by grounding the gate! >> >> Afaik you can blow the FETs by grounding the gate and then applying a >> large dU/dt on the drain. > >If I shut off the gate there MUST be a large change in drian voltage. >Well, large is relative, but at least the applied voltage. >Assuming the integral diode can clamp the inductive effects.... The substrate diode does not play here, it is reverse biased. It is exactly the same situation as when you exceed Vds by switching an inductive load off. If the device is fast enough it will suicide with the inductivity of the leads alone. Again the gate resistor would help to prevent this. The current that damages the device is supposed to appear though Cgd across the oxide whose gate side is held firmly low (missing gate resistor). I do not know for sure if this is what happens, but I know that it happens. {Quote hidden}> The coupling capacitance between D and G will >> produce enough voltage on the gate to breakdown the oxide (the inductance >> etc from the gate to the driver is enough for this). Is this what you mean >> ? >If the gate is well grounded, and the souce is well grounded, >how do I get gate voltage? >(If I had an inductive gate ground I can see it happening...) > >I have a demo with a 100 amp source of 12 volts to the drain. (MTM200N06) >was the FET. I have a load in the drain to supply to show the current. >1K2 watts. The Source is well grounded, the FET well Heat-sinked. I have >an external 15 volt zener from gate to source. I apply 10 volt charge to >the gate, all is well, 100 amps flow. (Disconecting the gate charge >source to show the charge remains on the gate...) I apply a 1/2 inch >piece of wire between the gate as source terminals to short the gate >charge... The FET fails! Gate to source short! Motorola said it's the >gate bonding wire which is inductiveenough to cause this. (They also had >a substrate explaination....) I have never used those FETs, but this is useful information. Thank you for sharing it. The failure mechanism seems to be similar to with what I describe at dU/dt above. Maybe it's the same thing that appears differently in different devices. Peter -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listservKILLspammitvma.mit.edu with SET PICList DIGEST in the body

On Thu, 11 Jul 2002 11:23:21 +1200 Jinx <joecolquittspam_OUTCLEAR.NET.NZ> writes: > > 2) Put a resistor in series with the gate to soften switching times > > > > Correct? > > For switching applications (ie the FET goes from fully off to fully > on > and vice versa).you want the complete opposite - fast clean > switching > times means the FET spends less time in its linear region which in > turn > generates less heat. I don't know if what is true for bipolar > transistors > is true for FETs - the most stressful time (generally) for a bipolar > is in > its linear region. Do FETs have SOAR diagrams ? > In one high voltage application a few years ago (a high speed FET blower), I found that a small resistor in series with the gate prevented transients from overvoltaging the gate. I believe that what was going on was lead inductance was causing a voltage spike on the source when the FET was turned on and off. Since this spike was not on the gate, there was a "relative spike" between the gate and the source, blowing out the gate. Adding the resistor allowed the gate to follow the source through the transient due to Cgs. I blew fewer FETs that way. The resistor was still pretty small, so the gate moved quickly. Harold FCC Rules Online at http://hallikainen.com/FccRules Lighting control for theatre and television at http://www.dovesystems.com Reach broadcasters, engineers, manufacturers, compliance labs, and attorneys. Advertise at http://www.hallikainen.com/FccRules/ . ________________________________________________________________ GET INTERNET ACCESS FROM JUNO! Juno offers FREE or PREMIUM Internet access for less! Join Juno today! For your FREE software, visit: dl.http://www.juno.com/get/web/. -- http://www.piclist.com hint: To leave the PICList @spam@piclist-unsubscribe-requestKILLspammitvma.mit.edu

On Thu, 11 Jul 2002, Jinx wrote: >> 2) Put a resistor in series with the gate to soften switching times >> >> Correct? > >For switching applications (ie the FET goes from fully off to fully on >and vice versa).you want the complete opposite - fast clean switching >times means the FET spends less time in its linear region which in turn >generates less heat. I don't know if what is true for bipolar transistors >is true for FETs - the most stressful time (generally) for a bipolar is in >its linear region. Do FETs have SOAR diagrams ? Yes ... but you really want to slow down the pulses on the FETs because they can really go ballistic. A 50kHz unsuppressed SMPSU radiating at 100+MHz is quite common if you don't. The FETs switch so fast that even the pigtail wires from the transformer to the drain have time to resonate. Peter -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics