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'[EE]: Microprocessor internal reset circuitry.'
2001\04\12@090038 by Russell McMahon

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I'm using a non-PIC microprocessor with no reset pin and a totally internal
power on reset and anti-brownout capability. Allegedly.
No confirmation or denial will be given to people guessing the processor
type and I'd rather people didn't guess in public at this stage :-).

The spec sheet states a Vdd voltage level below which the processor should
be in reset mode and above which it should be operational. No requirements
are placed on the rise time of Vdd to meet reset conditions.

In practice my mileage may and does vary.

Depending on batch and temperature code SOME of the processors do not reset
cleanly if the Vdd is raised slowly. It happens that slow and variable Vdd
rise times are an essential 'feature" of this environment unless I redesign
the circuit substantially. This problem varies with processor batch and has
only been identified recently.

All processors, whether "faulty" or OK, have their clocks start at about 2.2
volts and the internal reset circuit lets them start working at about 2.8
volts. The part is specced to run fro 3 to 5.5 volts. I am running a 5v
supply. Good processors and faulty processors can NOT be distinguished by
their clock starting action. This is NOT a clock starting
problem.

The requirement of coming out of reset cleanly with no limitation on Vdd
rise time is a strenuous one BUT I would think an essential one for a
processor with no reset line.


QUESTIONS:

1.    Is anyone else using a reset-line-less processor and does it always
work?

2.    What do people think about a processor failing in these admittedly
somewhat unusual circumstances.

3.    Any thoughts re work arounds. Fairly obviously I need to either "fix"
the processor or decrease the Vdd rise time. "Select on test" of good
processors is not an economically viable option. Fixing the rise time is
annoying as I have no control on the rise time of the input to the 5v
regulator. Adding extra components is an undesirable requirement at this
stage :-(.

4.    What should i say / would you say to the manufacturer (who doesn't
seem to yet really appreciate the problem as few if any other customers
would be troubled by it).

5.    What would you think of a processor that behaved like this?
I assume that in more normal circuits some of these will sometimes cause
problems. These problems would be hard to track down and there cause may
remain a mystery indefinitely.


TIA



     Russell McMahon
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2001\04\12@115323 by David W. Gulley

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face
Russell McMahon wrote:
 <SNIP>
> 5.    What would you think of a processor that behaved like this?
> I assume that in more normal circuits some of these will sometimes cause
> problems. These problems would be hard to track down and there cause may
> remain a mystery indefinitely.

 Short answer, I do not like it!
I have had similar problems with reset circuits (from various
manufacturers). In one case, adding bulk capacitance near the device
*helped*. It seems (in that case) if there were a power droop
immediately following the device coming out of reset (which happened due
to everything else "waking up"), the reset logic would shut down
thinking power had gone *bad*, and it would not come out of reset until
power was shut down and restored (with faster rise time).

Good Luck!

David W. Gulley
Destiny Designs

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2001\04\12@120604 by Olin Lathrop

face picon face
> The spec sheet states a Vdd voltage level below which the processor should
> be in reset mode and above which it should be operational. No requirements
> are placed on the rise time of Vdd to meet reset conditions.

In theory if they don't say it matters, than it shouldn't.  On the other
hand, they didn't come right out and give a rise time spec or say that it is
allowed to be infinitely slow.  I would consider this spec as "missing"
rather than interpret it that infinitely slow is OK.  I would talk to the
manufacturer.  If they are unwilling or unable to guarantee the infinite
rise time spec and deliver parts to that spec, then you have two choices:

1 - Use a different part if you can find one.

2 - Redesign the circuit to guarantee a maximum rise time.

I know you don't like either option, but that's where you're at.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, spam_OUTolinTakeThisOuTspamembedinc.com, http://www.embedinc.com

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2001\04\12@121410 by Bob Ammerman

picon face
> > The spec sheet states a Vdd voltage level below which the processor
should
> > be in reset mode and above which it should be operational. No
requirements
> > are placed on the rise time of Vdd to meet reset conditions.
>
> In theory if they don't say it matters, than it shouldn't.  On the other
> hand, they didn't come right out and give a rise time spec or say that it
is
{Quote hidden}

Unfortunately, option (2) is a bit bogus: without a rise time spec you'll
never know if your circuit is fast enough.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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2001\04\12@160136 by Dwayne Reid

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face
At 12:58 AM 4/13/01 +1200, Russell McMahon wrote:
>I'm using a non-PIC microprocessor with no reset pin and a totally internal
>power on reset and anti-brownout capability. Allegedly.
>No confirmation or denial will be given to people guessing the processor
>type and I'd rather people didn't guess in public at this stage :-).
>
>The spec sheet states a Vdd voltage level below which the processor should
>be in reset mode and above which it should be operational. No requirements
>are placed on the rise time of Vdd to meet reset conditions.
>
>In practice my mileage may and does vary.

You have my sympathies!

No easy answers from me, I'm afraid.  I've dealt with the problem in some
of my designs in 2 different ways and both require added parts.

1) Use a zener regulated supply, with a 4.3V zener in series with the base
of a PNP transistor.  The combination of the Vbe drop and zener voltage
gives me 5V.  Verbally: anode of zener to GND.  Cathode to base of
transistor.  Emitter of transistor to input supply via current limit
resistor.  4k7 resistor from B-E of transistor.  Collector of transistor to
PIC and rest of circuit.

The idea here is to take a slowly rising supply voltage and turn it into a
faster rising voltage.  A lot of my projects use a Zener regulated power
supply - this design adds only 2 parts to that and make for a much more
reliable power-up.

Another variation takes circuit power from the junction of the current
limit resistor and the transistor emitter (5V unswitched) and uses the
collector to drive MCLR (with a 22K pulldown resistor).  I use this version
whenever I have a MCLR pin available for use.

2) Use a 2 transistor power switch configured as a schmitt trigger.  It is
placed in series with whatever regulator I am using for that particular
project: either a zener or 3 terminal regulator.  It does not allow the
regulator to receive power until the input is well above the minimum
required and does not turn off until just above regulator dropout.  I will
sometimes add a 3rd transistor and load resistor to ensure I consume more
current while turned off than while the circuit is powered and operating.

dwayne



Dwayne Reid   <.....dwaynerKILLspamspam@spam@planet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
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2001\04\12@210146 by steve

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face
> > 2 - Redesign the circuit to guarantee a maximum rise time.

> Unfortunately, option (2) is a bit bogus: without a rise time spec
> you'll never know if your circuit is fast enough.

I couldn't say that I disagree with your comment but when you
think about it, a risetime spec for a reset circuit is rather bogus
itself.

If you consider an ideal situation, there is no need for time to come
into the situation other than sometime after the oscillator has
started and the pre-reset state is established. Other than that, the
requirement is purely voltage threshold based.

Add in some reality and you have the situation where a slowly
rising Vcc reaches the threshold point. At this point the micro is
most susceptible to noise. Any noise that exceeds the hysteresis
threshold will try to put the micro back into the reset state and if
that transition occurs within a minimum time (reset pulse width),
puts the micro into an undefined state. Also the act of the micro
coming out of reset makes it draw substantially more current, both
internally and with whatever is attached to the pins, again reducing
the effective hysteresis threshold.
To counteract this you can either ensure that the voltage is higher
by the time the current draw increases or lower the impedance of
the supply.

If you consider why a supply would rise slowly, it's generally
because it has a high impedance in there somewhere. So if you
give the micro a generous, low impedance source close by, the
effects of the slow risetimes are reduced locally. A capacitor to do
this has to be quite large because we are talking about lowering
the supply impedance over a much longer time period than the
10nF decoupling issues often discussed.

If you put say 47uF right next to the micro, you'll increase the
startup reliability for slow Vcc risetimes even though it is counter-
intuitive to add capacitance. However, as Bob says, you don't have
a figure to work towards as a spec so you can only improve and
not "fix" the problem with this approach.

So if I had a product where a slow risetime was an exception and
testing revealed that it could occur, I would be happy with this as a
fix. If a slow risetime was expected as the norm or a common
occurance, I would want to do something a bit more affirmative. In
that case I would look at something like a regulator with a
shutdown facility and use a zener to turn it on.

Steve.



======================================================
Steve Baldwin                Electronic Product Design
TLA Microsystems Ltd         Microcontroller Specialists
PO Box 15-680, New Lynn      http://www.tla.co.nz
Auckland, New Zealand        ph  +64 9 820-2221
email: stevebspamKILLspamtla.co.nz      fax +64 9 820-1929
======================================================

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