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'[EE]: Logic analyser trigger circuit.'
2002\06\20@130356 by lexandre_Guimar=E3es?=

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Hi,

   Does anyone have Tom Handley's 24 bit trigger circuit for a PLD archived
that could send to me ? I was not able to find where I put it and I am in
the proccess of making a small DSO and logic analyser and would love to take
a look at tha file. His site is down and I was not able to send email to him
also.

   I am trying to do a small thing that could be plugged to a palmtop and
help with field debugging. Most of the projects I see around are either too
fast or just deal with audio frequencies. I need something that can sample
at around 100 khz and can do somewhat complex triggering. I think a fast AVR
or Ubicom part with external SRAM should be able to achieve it with very
little circuit complexity.

Best regards,
Alexandre Guimaraes

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2002\06\20@134721 by Dwayne Reid

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At 02:02 PM 6/20/02 -0300, Alexandre Guimarães wrote:
>Hi,
>
>     Does anyone have Tom Handley's 24 bit trigger circuit for a PLD archived
>that could send to me ? I was not able to find where I put it and I am in
>the proccess of making a small DSO and logic analyser and would love to take
>a look at tha file. His site is down and I was not able to send email to him
>also.

From a private message:

From: Tom Handley <.....tomhandleyKILLspamspam@spam@mindspring.com>
Subject: Re: [PICLIST] [PIC]: ICSP Connector pinout?
In-Reply-To: <4.3.2.7.2.20020518125931.02218c00spamKILLspampop.telusplanet.net>> References: <.....5.1.0.14.2.20020517143454.009eeb70KILLspamspam.....mail.mindspring.com>>  <002401c1fda0$6f2d02a0$2e03010a@admin>
 <
EraseMEA90AF2166120624191A00C3BA07955A80821B7spam_OUTspamTakeThisOuTmfgncw2ke2ksvr1.mfgnc.corp>> Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

   Dwayne, my web site has moved to:

     
http://tomhandley.home.mindspring.com/wilbure.htm or...
      http://home.mindspring.com/~tomhandley/wilbure.htm

Hope this helps!

dwayne

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2002\06\21@155515 by Tom Handley

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   Alexandre, as Dwayne mentioned, my site has moved to:

      http://tomhandley.home.mindspring.com/wilbure.htm

   However, I would not bother with the old Lattice versions posted there.
I've been spending the last few months converting my Lattice and Mach
designs over to Xilinx... The Lattice parts are nearly obsolete, expensive,
and draw a `terrible' amount of current... It's frustrating as I've been
with Lattice for years and have their commercial Design Expert package, but
it's time to move on. At the low end, I'm using the Xilinx CoolRunner XPLA3
family, in particular, the XCR3064XL 64 macrocell device which comes in a
PLCC-44 package amongst others. This is similar to the Lattice ispLSI1016E
yet it draws a fraction of the current and is priced about 75% less. It has
a 3.3V core with 5V tolerant I/O. I use a low-dropout, 3.3V linear regulator
in a TO-92 or surface mount package. These regulators are widely available
and low cost. Also, putting a regulator right at the device has other
obvious benefits. You can order these devices directly from Xilinx in single
and small quantities. The last order I placed was last month and they were
still around $6.50/ea + $10 shipping in the USA.

   Lattice's Design Expert package and Xilinx's WebPACK are similar since
the same companies provide the tools (Verilog, VHDL, ModelSim, etc) so
moving from one to the other is fairly easy but you will still have some
homework to do as each vendor adds their own `twist' on things and then
there is the differences in architecture which require a different set of
constraints, fitter reports, timing analysis, simulation, etc. If you have
used Lattice's schematic capture package you will find some similarities but
it's really a different package and takes some getting use to, if for no
other reason, to `un-learn old habits' from the former. One thing that
immediately struck me is that you can not lock pins at the schematic level
but the Chip Viewer makes it easy to assign pins and you can always edit the
pin constraints file which is what I prefer after letting the fitter make an
initial pass. The overall flow of the Project Navigator is very similar.

   For JTAG programming, the Xilinx cable is a simple buffered parallel
port interface and a reference schematic is available on their site. Unless
you plan on using 1.8V core devices (ie: CoolRunner II), the cable will work
fine with 3.3V and 5V devices. If you looked at the Lattice ISP Download
cable schematic, this is similar. They use two 74HC125s and some passives.
Regarding dual-use of the JTAG pins, in the Lattice device, you have the
option of reserving the JTAG pins at the sacrifice of 4 dedicated inputs.
This is set as part of the properties during the fitting process. In the
CooolRunner devices, there's an external Port-Enable pin which I prefer.

   Finally, if you or anyone else are interested in the Xilinx family and
designing their own CPLDs, first go to their site and download WebPACK and
all the manuals, app notes, JTAG cable schematic, etc.

      http://www.xilinx.com/

   Then, go directly to:

      http://www.al-williams.com/pictutor/

   I can not believe I have not run across Al's site before! On there, Al
has provided an `Absolutely Outstanding' tutorial on using WebPACK with
Xilinx's XC95 devices. He also has a nice protoboard to get you up to speed
quickly. His tutorial applies directly to many of the Xilinx devices and he
even touches on Verilog and ModelSim with examples, two very complex
subjects in their own right. I wish I had know about this several months ago
as I had to do it the `old fashioned way'... RTFManuals ;-)

   You will still have a lot of studying to do, especially if you are new to
this but Al's site can really help you get up to speed with simple,
practical examples. He obviously has a great deal of experience with Xilinx,
Altera, and CPLDs in general.

   Great work, Al!

   - Tom

At 10:02 20-06-02, Alexandre Guimarães wrote:
{Quote hidden}

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2002\06\21@194817 by Tom Handley

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   Alexandre, I just realized I didn't answer your original question ;-)

   I have not ported the Trigger comparator to the XCR3064XL yet but it
will be trivial. The last revision I had posted is a 28-Bit version using a
Lattice ispLSI1016E but as I mentioned earlier, I would not use those
versions. Using the Xilinx devices, I've improved on the port expander, SRAM
controllers and other designs. Back to the comparator, I want to try and get
a full 32 Bits with the Xilinx part. Give me a day or few and I'll get back
to you. As usual, I have not had much spare time but I'm committed to it...

   One little `pet' project is an 8-Bit Logic Analyzer core using the above
device. It would allow expansion in banks of 8 channels, each with their own
clock source or combined with other banks. The core includes an 8-Bit
Trigger comparator with Bit-enables, 15-Bit free running SRAM address
counter, control logic (ARM, TRIG, etc), and a 15-Bit post Trigger counter.
It is designed to support fast 32KByte SRAM. I'm having doubts about fitting
the post trigger counter but I'm willing to make some compromises. Right now
I'm studying various counters implemented in Verilog. A simple ripple
counter obviously won't do due to the propagation delays. One thing for
sure, no one will be satisfied with it as it stands. There are just too many
trade-offs to be made and there is a good reason commercial units costs a
fortune... However, simple data capture with fairly versatile trigger and
clock options can go a long ways. Also, once you have the core, you have the
foundation for a DSO by adding the analog front-end. With each bank having
it's own clock, this provides for some interesting combinations of digital
and analog data capture. Right now, I'm planning on a second CPLD to handle
the `glue logic' to support up to 4 banks or 32-Bits as well as the host
interface.

   You mentioned using a "palmtop". One of the advantages of these devices
are their low current consumption. From the data sheet, at 20MHz it draws
around 4ma, around 200ua at 1MHz, and near 0ma when static. This obviously
depends on the design. The Lattice device draws around 60-90ma... The Mach
devices were an improvement but the equivalent parts did not have the extra
4 inputs which I relied upon for some designs like the Trigger comparator.
Also, these devices are faster, comming in 6, 7, and 10ns versions. The
$6.50 price I mentioned in my previous message was for the 6ns version. The
10ns version is only $3.20. You can find the Xilinx on-line store at:

     http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/EN/Catalog

   - Tom

At 10:02 20-06-02, Alexandre Guimarães wrote:
{Quote hidden}

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2002\06\21@202600 by lexandre_Guimar=E3es?=

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Hi, Tom

>     One little `pet' project is an 8-Bit Logic Analyzer core using the
above
> device. It would allow expansion in banks of 8 channels, each with their
own
> clock source or combined with other banks. The core includes an 8-Bit
> Trigger comparator with Bit-enables, 15-Bit free running SRAM address
> counter, control logic (ARM, TRIG, etc), and a 15-Bit post Trigger
counter.
> It is designed to support fast 32KByte SRAM.

   Yes, Yes, Yes and Yes... That is exactly the kind of thing I would just
love to put my hands on :-) I have to do much debugging in the field and
have had many times where I was inside a train or a bus modifying progams
and would love to have any scope or logic analyser in my hands !! Most
professional instruments are too big and need to be plugged to the AC line.
I have a bitscope that I adapted to be used with batteries but it is still
very ackward to get everything plugged and running. My dream is a small 10
bits scope and 8 or 16 channels logic analyser that I can plug to the
palmtop and see my signals changing all around. It would make life so much
easier !

> There are just too many
> trade-offs to be made and there is a good reason commercial units costs a
> fortune...

   It all depends on the application. I would not learn to live without my
100 megs digital scope but I do not need it most of the time. A small
instrument that I can taylor to my needs would be very welcome. I could
change the program to capture in a different way or show the results upside
down if I needed it ! I cannot do it with my gagescope and it is impossible
to use inside a running bus ! Specially if I make a mistake and cut the
engine suddenly :-) I have done that and my laptop and bitscope flew to the
floor :-(

> However, simple data capture with fairly versatile trigger and
> clock options can go a long ways.

   If we could trigger using 2 words in a sequence it would make the
instrument even more valuable. That would help a lot to debug programs and
get a nice trigger signal for the scope. Not essencial but nice. I would not
mind having the memory as a circular buffer and have the trigger point
always in the middle of the captured memory or have it at a fixed position.
The post trigger size could be fixed to make the design easier. If we have
enough memory the clock options can be simpler also.

>     You mentioned using a "palmtop". One of the advantages of these
devices
> are their low current consumption.

   Small batteries would make it even more usable. I could have the board
with PLD's, analog front end and microcontroller in a small box with some
NiCd's and the palmtop over the serial cable. Wow, that is a dream :-) It
could sit on my desk and I could get the oldie scope and let it sit under
the desk and I could keep both my hands to hold myself when I get inside
moving things !

Best regards,
Alexandre Guimaraes

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2002\06\21@203234 by lexandre_Guimar=E3es?=

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Hi, Tom


>     Alexandre, as Dwayne mentioned, my site has moved to:
>
>        http://tomhandley.home.mindspring.com/wilbure.htm
>
>     However, I would not bother with the old Lattice versions posted
there.
> I've been spending the last few months converting my Lattice and Mach
> designs over to Xilinx... The Lattice parts are nearly obsolete,
expensive,
> and draw a `terrible' amount of current...

   Thanks a lot for the insight and pointers. I was looking for your
designs specially because they were tested and debugged ! I know how hard it
is to debug anything. I am planning on making just a few instruments and the
parts cost would not be the worst part of it. I was thinking about looking
at how you did it and making all the logic in a single PLD but I found out
the your page just has the JED files for burning the parts :-( Would it be
possible to get the schematics or VHDL source ? I am not planning a
comercial product and can give the modifications to a new chip back to you.
I think a small design that makes a 100 khz 10 bit scope and 16 bits logic
analyser would be usefull for many people. Even more if I could expand you
design and have it sorting based on 2 different samples. That way we could
get a nice trigger on a specific sequence. I almost never use more than 100
khz sampling rate on my digital scope for simple embeeded design !! I am new
to the PLD World but with your pointers I should get up to speed faster. I
have used PLD's in some designs but always had someone else doing the PLD
design for me.

Best regards,
Alexandre Guimaraes

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2002\06\22@004232 by John Dammeyer

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Hi,

Any comments on Verilog verses VHDL for a first timer?   I need to
create some customized CAN bus bit streams and a Xilinx part seems like
it just might be the answer.

John Dammeyer


Wireless CAN with the CANRF module.
www.autoartisans.com/documents/canrf_prod_announcement.pdf
Automation Artisans Inc.
Ph. 1 250 544 4950


> {Original Message removed}

2002\06\23@173827 by Mike Singer

picon face
.
John Dammeyer wrote:
> Any comments on Verilog verses VHDL for a first timer?   I need to
> create some customized CAN bus bit streams and a Xilinx part
> seems like  it just might be the answer.

From:
"HDL basic training: top-down chip design using Verilog and VHDL"
Douglas J Smith, VeriBest 1996 (big article)
.
.
.
 Ease of learning. If you have no knowledge of either
language, Verilog is probably easier to grasp and understand.
This statement assumes the exclusion of the Verilog compiler
directive language for simulation and of the PLI. If you include
these two, consider them additional languages you need to
learn. Also, VHDL may seem less intuitive at first for two reasons.
First, it is very strongly typed, a feature that makes it robust
and powerful for an advanced user after a longer learning
phase. Second, there are many ways to model the same
circuit, especially one with large hierarchical structures.
.
.
.

Other sources:
www.angelfire.com/in/verilogfaq/index.html
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html

 Mike.

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2002\06\25@111714 by Tom Handley

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At 17:24 21-06-02, Alexandre Guimarães wrote:
...
>    If we could trigger using 2 words in a sequence it would make the
>instrument even more valuable. That would help a lot to debug programs and
>get a nice trigger signal for the scope. Not essencial but nice. I would not
>mind having the memory as a circular buffer and have the trigger point
>always in the middle of the captured memory or have it at a fixed position.
>The post trigger size could be fixed to make the design easier. If we have
>enough memory the clock options can be simpler also.

   Alexandre, these types of add-ons are part of what doomed my earlier
project a few years ago. It collapsed under its own weight ;-)

   I want to keep the trigger path as short as possible. When you consider
the delays from the pod buffer to the trigger comparator, to the control
logic to the SRAM, the maximum sample rate drops dramatically...

   By providing a basic core optimized for speed, folks can add any features
they desire. In your example above, you can still add multiword triggering.
Just send it's final trigger output to the core. Another example is the
clock. Setting the polarity, source, etc, will be handled external to the
core. I could easily add such features but every inverter/gate/register adds
Xns to the path... I want to leave these decisions up to the user. Since I
want 32-Bit capture, I'll be doing a `glue' chip to provide special features
but in the end, it will still be just one version tailored to my needs and
by its nature, full of compromises. This may or may not be useful to others
but I'll be glad to share it.

   - Tom

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2002\06\25@121426 by Tom Handley

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   John, I'm fairly new to VHDL and Verilog. Mark Singer's comments sum it
up well. Most of my work has been with schematic capture and ABEL. A couple
of years ago I started studying VHDL. However, Verilog seemed more natural
for me. While this is a crude comparison, I would think someone with a
strong software background (ie: CS major) probably would be more comfortable
with VHDL. It kind of reminds me of PASCAL or Modula II. For someone like
myself with a strong hardware background and use to programming in C,
Verilog is fairly easy to learn. Aside from what you are comfortable with,
it's important to consider what you want to do now and in the future. VHDL
is a powerful language that goes beyond simple hardware description. Verilog
is more constrained and tightly focused on hardware. Search Google using
"VHDL Verilog compare" and you will find a wealth of info. Note, there is
now a third standard emerging from the two but the name escapes me right
now. I think EDN or one of the newsletters had an article on it a few months
ago.

   Here are some books I started with:

      The Designer's Guide to VHDL
      Peter J. Ashenden
      ISBN: 1-55860-270-4

   Fairly thorough coverage of the language with an eye towards hardware.

      VHDL Starter's Guide
      Sudhakar Yalamanchili
      ISBN: 0-13-519802-X

   Covers the basics and applications in digital design.

      Verilog HDL Synthesis - A Practical Primer
      J. Bhasker
      ISBN: 0-9650391-5-3

   By no means a language reference, it quickly covers the basics and moves
on to real-world hardware examples. This little book has been a big help in
getting up to speed quickly and generating useful code. I still intend to
get a good Verilog reference, but if you have some experience in this area,
I highly recommend this book as part of your library.

   - Tom

At 21:18 21-06-02, John Dammeyer wrote:
>Hi,
>
>Any comments on Verilog verses VHDL for a first timer?   I need to
>create some customized CAN bus bit streams and a Xilinx part seems like
>it just might be the answer.
>
>John Dammeyer

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2002\06\25@130634 by Alan B. Pearce

face picon face
>>    If we could trigger using 2 words in a sequence it would make the
>>instrument even more valuable. That would help a lot to debug programs and
>>get a nice trigger signal for the scope. Not essencial but nice. I would
not
>>mind having the memory as a circular buffer and have the trigger point
>>always in the middle of the captured memory or have it at a fixed
position.
>>The post trigger size could be fixed to make the design easier. If we have
>>enough memory the clock options can be simpler also.

>    Alexandre, these types of add-ons are part of what doomed my earlier
>project a few years ago. It collapsed under its own weight ;-)

>    I want to keep the trigger path as short as possible. When you consider
>the delays from the pod buffer to the trigger comparator, to the control
>logic to the SRAM, the maximum sample rate drops dramatically...

The way to expand your triggering is to use high speed static RAM chips. I
have at home somewhere an article in an HP Journal that they did for a logic
analyser where they did this. The RAM chips were loaded with a pattern that
allowed the address lines to be used as the trigger bit inputs, and the data
outputs as the trigger detection outputs. If you use byte wide devices then
8 conditions can be set, and the trigger width is expanded in address line
count increments.

This minimises the trigger input to detect output delay to just the access
time of the RAM plus any OR logic at the output, which should be no more
than 2 gates deep using modern GAL chips, or it could be another 1 bit wide
RAM. The RAM chips are then loaded from your control microprocessor, a PIC
of course. :)) This allows setting all sorts of conditions, including "don't
care" states into your trigger requirements.

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2002\06\26@120613 by Tom Handley

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   Alan, I'm using high speed 32KByte SRAM of the type found in L2 caches.
These are 28-Pin x 0.3" devices and are available from many sources. As far
as the HP article, I would really like to take a look at that. If you can
find which issue of the HP Journal that was in, please let me know. I have
never heard of anything like this but considering it's source, I'd like to
check it out. Thanks,

   - Tom

At 10:06 25-06-02, Alan B. Pearce wrote:
I wrote:
{Quote hidden}

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2002\06\26@123001 by Alan B. Pearce

face picon face
>Alan, I'm using high speed 32KByte SRAM of the
>type found in L2 caches. These are 28-Pin x 0.3"
>devices and are available from many sources. As far
>as the HP article, I would really like to take
>a look at that. If you can find which issue of
>the HP Journal that was in, please let me know. I have
>never heard of anything like this but considering
>it's source, I'd like to check it out. Thanks,

OK I will see if I can look it out tonight. I think I know where my stash of
HP-J's is.

Those would certainly be the ideal RAM chip to use for this application.

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2002\06\27@042418 by Alan B. Pearce

face picon face
>If you can find which issue of the HP Journal that
>was in, please let me know. I have never heard of
>anything like this but considering it's source,
>I'd like to check it out. Thanks,

Right, had a dig in the archives, and the one I remember is the January 1977
issue, dealing with the 1611A Logic Analyzer. The specific diagram I
remember is on the bottom of page 9, with a description of the internal
workings of the RAM in the upper diagram on the same page.

You may also find some useful info in a couple of articles in the February
1978 issue, although these are less related to hardware design, more the
internal software.

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'[EE]: Logic analyser trigger circuit.'
2002\11\13@021120 by David Harris
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Hi Tom-
Did you get any further with the Logic Analyzer?
David

Tom Handley wrote:

{Quote hidden}

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2002\11\14@142401 by Tom Handley

picon face
   David, I've been busy dealing with my mother's estate so things have
been on hold. In anticipation of getting back into it (and back to work)
I just ordered Xilinx's Parallel Cable IV. I've built a version based on
their earlier cable but decided to get the commercial version as I
upgrade several tools. I'll share any progress when I get back into it.

   - Tom

At 22:45 12-11-02, David wrote:
>Hi Tom-
>Did you get any further with the Logic Analyzer?
>David
>
>Tom Handley wrote:

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