Searching \ for '[EE]: I2C questions' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/i2cs.htm?key=i2c
Search entire site for: 'I2C questions'.

Exact match. Not showing close matches.
PICList Thread
'[EE]: I2C questions'
2001\02\01@125608 by Andre Abelian

picon face
Hi to all engineers,

I have 3 questions about I2C.

start condition

1. while clock is high  and  high to low transition on SDA line is Start
Condition right ?


acknowledge

   transmitter or receiver leaves SDA and SCL lines high for the device to
acknowledge
   and the device must pull SDA line to low while SCL line is high right ?
if this is true
   then we have duplicated same start condition other devices connected on
same bus
   may  not function properly. My question is is this how acknowledge
condition
  works ?

2. Arbitration

the purpose of arbitration is when there are more then one masters
connected to the bus to prevent simultaneous control make sure they do not
drive
same slave at the same time by comparing address byte. my question is
how each master is programmed to recognize this condition. To my
understanding right after start condition all devices connected on the bus
compares the address if it matches with slave device then it will
acknowledge
and at the same time if master matches too then it must terminate it self.

3. 10 bit addressing

if  112 devices are the limit then what is point of
using 10 bit addressing

any help how  acknowledge, Arbitration and 10 bit addressing  works will
highly appreciated.

Andre

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\01@134613 by Mike Mansheim

flavicon
face
>1. while clock is high  and  high to low transition on SDA line is Start
>Condition right ?

Yes.

>acknowledge

>    transmitter or receiver leaves SDA and SCL lines high for the device
to
>acknowledge
>    and the device must pull SDA line to low while SCL line is high right
?

No.  The device must pull SDA low such that it is stable low during the ack
clock pulse.  The rule is that SDA never changes state while SCL is high
except to signal starts and stops.

>2. Arbitration

>the purpose of arbitration is when there are more then one masters
>connected to the bus to prevent simultaneous control make sure they do not
>drive
>same slave at the same time by comparing address byte. my question is
>how each master is programmed to recognize this condition.

Arbitration is on a bit by bit basis - it can happen anywhere in the bit
stream, and is NOT related to the address byte.  On the i2c bus, a high
is "asserted" by releasing the line and letting it float high via the
pull-ups.  A low is asserted by driving the line low.  If two masters
generate a start condition at the same time, "arbitration" is used to
determine which one gets the bus.  This is determined the first time the
two want to put a different value on SDA.  The one putting a "zero" on
SDA wins.  This is done by each master checking SDA each time it wants a
"one" on SDA:  if a "zero" is read, then that master must get off the
bus (by simpling releasing both lines, NOT by generating a stop).  This
works because a master can't force a one, only a zero.
Clock stretching works in much the same way - when a master wants to start
a
clock pulse, it releases SCL high.  By waiting until SCL actually goes
high, that master will wait until all devices on the bus are ready -
because any of them can force SCL low.

>3. 10 bit addressing

Never used it, but the i2c bus specification from Phillips discusses it.

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\01@145017 by Andre Abelian

picon face
Mike,

thanks for you replay

I still do not get it

> No.  The device must pull SDA low such that it is stable low during the
ack
> clock pulse.

my question is befor and after pulling SDA low where the SCL was ?


> The rule is that SDA never changes state while SCL is high
> except to signal starts and stops.
>
> >2. Arbitration
>
> >the purpose of arbitration is when there are more then one masters
> >connected to the bus to prevent simultaneous control make sure they do
not
{Quote hidden}

Andre

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\01@162128 by Mike Mansheim

flavicon
face
>my question is befor and after pulling SDA low where the SCL was ?

Master drives SCL low after 8th clock pulse; has to remain low for
specified time (4.7 us? don't remember).  Just after driving SCL
low, master releases SDA (makes it an input) so device can control
it.  If the device is going to ack, it has to drive SDA low while
SCL is low.  Master executes 9th clock pulse; looks at SDA during
the pulse (i.e. while SCL is high).  If SDA is low, then it has
received the ack.
If the device knows that it is not going to have enough time to
decide if an ack is appropriate, then it can hold SCL down until
it is ready to either drive SDA down or release it high.  This is
clock stretching - when the master releases SCL high for the 9th
clock pulse, it needs to wait until SCL has actually gone high,
which will happen when the device releases SCL.
One of the things that makes this bus work is that any device can
drive (or hold) SCL and SDA down.

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\01@184605 by Andre Abelian

picon face
Mike,

your explanations made me to understand perfectly about ack.
I still have 1 more question unclear about arbitration again.
you said arbitration is bit by bit basis and it can be anywhere.
My question is let say there are 2 masters on line and each master is
going to send 256 byte of data how can 1th master know about what 2th
master is going to send or what rule is used to determine the error is there
any other way of explaining about it.

thanks in advance

Andre


{Quote hidden}

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\01@214849 by Bob Ammerman

picon face
----- Original Message -----
From: Andre Abelian <spam_OUTengelecTakeThisOuTspamEARTHLINK.NET>
To: <.....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU>
Sent: Thursday, February 01, 2001 7:16 PM
Subject: Re: [EE]: I2C questions


> Mike,
>
> your explanations made me to understand perfectly about ack.
> I still have 1 more question unclear about arbitration again.
> you said arbitration is bit by bit basis and it can be anywhere.
> My question is let say there are 2 masters on line and each master is
> going to send 256 byte of data how can 1th master know about what 2th
> master is going to send or what rule is used to determine the error is
there
> any other way of explaining about it.
>

Let me tackle it this time.

Basically both masters assume that they are in control. As they send bits
(address or data) they compare what they are trying to send to what is
actually on the bus.

At some point, assume master A is trying to send a 0 and master B is trying
to send a 1.

Master B notices that the bus has been pulled low and thus knows that some
other master is on the bus, and thus it (master B) has lost arbitration.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2001\02\02@100727 by Olin Lathrop

face picon face
> 1. while clock is high  and  high to low transition on SDA line is Start
> Condition right ?

Yup.

> acknowledge
>
>     transmitter or receiver leaves SDA and SCL lines high for the device
to
> acknowledge
>     and the device must pull SDA line to low while SCL line is high right
?

No.  First, the master always drives SCL, regardless of whether it is the
receiver or the transmitter.  Second, the receiver always produces the ACK
bit.  This means the transmitter releases SDA for the ACK bit and the
receiver pulls it low to ACK the byte it just received.  Note that if a
non-existant device is addressed, then SDA will just float high, thereby
producing a NACK.

Third, SDA must only be changed while SCA is low for normal data transfer.
Changing SDA while SCA is high signals either a start or stop condition.
For a normal data bit transfer, the master drives SCA low to signal the end
of the previous bit, the transmitter (of that bit) should then put the bit
value on SDA as soon as possible, then the receiver of the bit latches the
bit value from SDA on the rising edge of SCA.

{Quote hidden}

Multi master is more complicated than I want to get into here.  Read data
sheet for the MSSP module.  The IIC interactions are explained there fairly
well.  There is also more background information on the Microchip and
Phillips web sites, and many other places.


*****************************************************************
Olin Lathrop, embedded systems consultant in Devens Massachusetts
(978) 772-3129, olinspamKILLspamembedinc.com, http://www.embedinc.com

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics


More... (looser matching)
- Last day of these posts
- In 2001 , 2002 only
- Today
- New search...