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'[EE]: How to retain RAM data when power is off?'
2001\10\17@113856 by John Waters

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Hi All,

My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used for
storing some important data I want to retain even when the power is off.
What is the normal way to retain data on RAM? Is using a battery the best
solution? If so, how do I turn on the battery "only" when the power is off?

Thanks in advance!

John




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2001\10\17@123125 by Ned Konz

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On Wednesday 17 October 2001 08:37 am, John Waters wrote:
> Hi All,
>
> My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used for
> storing some important data I want to retain even when the power is off.
> What is the normal way to retain data on RAM? Is using a battery the best
> solution? If so, how do I turn on the battery "only" when the power is off?

Sometimes there is just a diode between the battery and the V+ of the RAM.
There are also single-chip power monitoring chips that take care of the chip
select, etc. when the power is going up or down (remember that you don't want
to have writes to the chip enabled when the microprocessor is not running
properly). Some of these (as I recall) provide a power output for battery RAM
as well.

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2001\10\17@160227 by Mike Hardwick

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>My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used for
>storing some important data I want to retain even when the power is off.
>What is the normal way to retain data on RAM? Is using a battery the best
>solution? If so, how do I turn on the battery "only" when the power is off?

John,

I've used Analog Devices' ADM695 more than once for jobs like this. It
handles backup battery switchover as well as chip select gating and a few
other functions that are very useful in most small embedded systems. It has
performed flawlessly...

Mike Hardwick, for Decade Engineering -- <http://www.decadenet.com>
Manufacturer of the famous BOB-II Serial Video Text Display Module!

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2001\10\17@160814 by Chetan Bhargava

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Apart from adding a low-drop diode between battery and 62256 you should also
make sure that when there is no power in your circuit you should have the
/ce at high logic level. When /ce is high the device (62256LP) takes
micro-amps to retain the contents.

You can also use a small ni-cd battery (3.6v) and add a trickle charge
circuit.


{Original Message removed}

2001\10\17@203641 by 859-1?Q?Alexandre_Guimar=E3es?=

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> I've used Analog Devices' ADM695 more than once for jobs like this. It
> handles backup battery switchover as well as chip select gating and a few
> other functions that are very useful in most small embedded systems. It
has
> performed flawlessly...


   Dallas also has some nice devices like the DS1210.

Best regards,
Alexandre Guimaraes

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2001\10\18@010755 by SM Ling

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> >My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used
for
> >storing some important data I want to retain even when the power is off.
> >What is the normal way to retain data on RAM? Is using a battery the best
> >solution? If so, how do I turn on the battery "only" when the power is
off?

Dallas has a RAM chip with built-in battery for exactly this purpose.  You
might want to check it.

Cheers, Ling SM

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2001\10\18@015544 by Vasile Surducan

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The cheapest way to turn on the battery when the power is off is to use a
diode. Also a small pnp + 3 resistors  current charge is required when
accu is used. I think you can't find a chip less expensive than all this
devices.
Vasile

On Wed, 17 Oct 2001, John Waters wrote:

{Quote hidden}

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2001\10\18@030453 by Jean-Michel Howland

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>My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used for
>storing some important data I want to retain even when the power is off.
>What is the normal way to retain data on RAM? Is using a battery the best
>solution? If so, how do I turn on the battery "only" when the power is off?

Texas Instruments have some nice SRAMs with in-built backup battery.

http://focus.ti.com/docs/browse/productnavigation.jhtml?familyId=473&tfsection=products&templateId=2

Also SRAMs with RTC and in-built crystal & battery.

http://www-s.ti.com/cgi-bin/sc/family3.cgi?family=REAL-TIME+CLOCKS

The really nice thing is you can order free samples. :-)

Regards
Jean-Michel.

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2001\10\18@081540 by 742-9014

face picon face
> > >My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used
> for
> > >storing some important data I want to retain even when the power is
off.
> > >What is the normal way to retain data on RAM? Is using a battery the
best
> > >solution? If so, how do I turn on the battery "only" when the power is
> off?
>
> Dallas has a RAM chip with built-in battery for exactly this purpose.  You
> might want to check it.

You could also look into serial EEPROM if you have warning before power will
go down or can back up at regular intervals.  One 8 pin IIC chip can hold
32K x 8.


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2001\10\18@115430 by Harold M Hallikainen

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       We designed a couple products around the Dallas RamPort, which is a
battery backed RAM with built in latches to latch out the addresses. They
then discontinued it. I don't use single sourced Dallas parts any more.
Of course, then Maxim bought Dallas, but I've never had that problem
(yet) with Maxim...

Harold


On Thu, 18 Oct 2001 12:16:02 +0800 SM Ling <RemoveMEpiclisterspamTakeThisOuTYAHOO.COM> writes:
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2001\10\18@115434 by Harold M Hallikainen

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       I've generally used a 1F capacitor that is charged through a diode and
current limit resistor from the +5V supply. I then use a Dallas/Maxim
1210 to handle power switching. You also route the chip select to the RAM
through the 1210 to prevent any reads or writes during power down. Write
are obviously a problem, corrupting RAM. Reads are also  a problem since
the data lines would then attempt to power the powered down PIC, quickly
discharging your battery or capacitor.

Harold


On Wed, 17 Oct 2001 08:37:28 -0700 John Waters
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2001\10\18@122439 by Robert Rolf

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And we found that the Dallas RAMCLOCK parts didn't live up to their
claimed 10 year life. Most died after 6 years. All were dead by 8 years.
The only problem we've had with Maxim is GETTING parts. The lead time
on some stuff is ludicrous.

Give the life cycle time on some of the serial EE parts, (1 million
plus cycles) I'd be inclined to use non-volatile memory (EEPROM).
There is even a product out there that has RAM (for speed) which
gets automatically initialized from shadow EEPROM, but I don't remember
who makes it.

R

Harold M Hallikainen wrote:
{Quote hidden}

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2001\10\18@140606 by Byron A Jeff

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On Thu, Oct 18, 2001 at 08:25:18AM -0700, Harold M Hallikainen wrote:
>         I've generally used a 1F capacitor that is charged through a diode and
> current limit resistor from the +5V supply. I then use a Dallas/Maxim
> 1210 to handle power switching. You also route the chip select to the RAM
> through the 1210 to prevent any reads or writes during power down. Write
> are obviously a problem, corrupting RAM. Reads are also  a problem since
> the data lines would then attempt to power the powered down PIC, quickly
> discharging your battery or capacitor.

This discussion seems to be going on in 3 or 4 threads at the same time.
I posted the same basic question but got no responses.

Here's my question: Why not skip the RAM supervisor, and simply power the
PIC along with the RAM? Put the PIC into sleep after it completes a read or
write, with the CE held high. Then you have no write corruption, the PIC
continues to be powered for the duration, and is only draws microamps in
sleep mode.

This was my plan. I was concerned about doing a partial power down because
I plan to have latches inbetween the RAM and the PIC. But there should be
no power draw if all of the inputs/outputs of the latches are tri-stated?
Right?

The task here is on my short list. Looking forward to some more discussion
on the subject.

BAJ

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2001\10\18@142528 by asena

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Why dont you use a FRAM ?

They're very nice NVRAM, that write at the same speed as the bus.

Sena







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2001\10\18@150416 by Byron A Jeff

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On Thu, Oct 18, 2001 at 07:23:20PM +0100, Antonio Sergio Sena wrote:
> Why dont you use a FRAM ?
>
> They're very nice NVRAM, that write at the same speed as the bus.

Be aware that FRAM wears on reads in addition to writes. And while the number
of accesses can be quite high, it is finite.

The other issues are always cost, availablility, and product lifetime in terms
of manufacturers keeping a part available.

Personally I'd go with the EEPROM unless write speed/endurance were a
significant issue.

BAJ
> > And we found that the Dallas RAMCLOCK parts didn't live up to their
> > claimed 10 year life. Most died after 6 years. All were dead by 8 years.
> > The only problem we've had with Maxim is GETTING parts. The lead time
> > on some stuff is ludicrous.
> >
> > Give the life cycle time on some of the serial EE parts, (1 million
> > plus cycles) I'd be inclined to use non-volatile memory (EEPROM).

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2001\10\18@152046 by Matt Pobursky

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On Thu, 18 Oct 2001 14:04:01 -0400, Byron A Jeff wrote:
>
>This discussion seems to be going on in 3 or 4 threads at the
>same time.
>I posted the same basic question but got no responses.
>
>Here's my question: Why not skip the RAM supervisor, and simply
>power the
>PIC along with the RAM? Put the PIC into sleep after it
>completes a read or
>write, with the CE held high. Then you have no write corruption,
>the PIC
>continues to be powered for the duration, and is only draws
>microamps in
>sleep mode.

It should work. I just checked a Samsung SRAM datasheet and it
says as long as CS1* > Vcc-0.2V, CS2 > Vcc-0.2V or CS2 < 0.2V,
Other inputs=0~Vcc, then you will be in low power standby.

>This was my plan. I was concerned about doing a partial power
>down because
>I plan to have latches inbetween the RAM and the PIC. But there
>should be
>no power draw if all of the inputs/outputs of the latches are
>tri-stated?
>Right?

As long as you are using HC (or some other high speed CMOS)
latches and not switching them, they'll draw very low microamps.
The only thing to watch for is leakage currents in/out of the
SRAM address and data pins. The data pics of the SRAM will be
Hi-z so I don't think they'll be a problem. I'm not sure what the
address lines look like, but I'm guessing they look like Hi-z
CMOS inputs. You should be able to use a PIC port pin as a
tri-state signal when you "go to sleep".

Signals between your PIC and the buffer/latch inputs should be
only CMOS level leakages (very low microamps) when not switching
also.

>The task here is on my short list. Looking forward to some more
>discussion
>on the subject.

I think it should work fine. Keep us posted, I'm interested what
you come up with.

Matt Pobursky
Maximum Performance Systems

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2001\10\18@153103 by Harold M Hallikainen

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       Keeping the PIC powered but asleep is an interesting approach. You'd
then have to generate an interrupt or something to wake it up.  I guess
you could tie RB0/INT to an unbacked supply. Generate an interrupt on it
going high, taking the processor out of sleep. In the main loop, if RB0
is low, go into sleep.
       What about the watchdog timer? I like using a watchdog, but this will
wake the processor, for a short time, every 2 seconds or so. Even for a
short time, this probably takes a lot more energy than an unclocked SRAM.
       Interesting approach, though. I like it because of the lower parts count
("The ideal design has zero parts.")

Harold



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2001\10\18@154641 by Byron A Jeff

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On Thu, Oct 18, 2001 at 12:13:25PM -0700, Harold M Hallikainen wrote:
>         Keeping the PIC powered but asleep is an interesting approach.

Glad you like it.

> You'd
> then have to generate an interrupt or something to wake it up.  I guess
> you could tie RB0/INT to an unbacked supply. Generate an interrupt on it
> going high, taking the processor out of sleep. In the main loop, if RB0
> is low, go into sleep.

That's the basic idea. The PIC would go to sleep when power isn't applied and
be woken up when power is applied.

>         What about the watchdog timer? I like using a watchdog, but this will
> wake the processor, for a short time, every 2 seconds or so. Even for a
> short time, this probably takes a lot more energy than an unclocked SRAM.

True. But the difference is that a watchdog will only bring the PIC out of
sleep, not reset it. But cranking up the oscillator will suck up some juice.

>         Interesting approach, though. I like it because of the lower parts count
> ("The ideal design has zero parts.")

Essentially there should only be one or two additional parts: the steering
diode for the battery, and possibly a MOSFET switch to remove power from the
other parts of the circuit.

BAJ
{Quote hidden}

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2001\10\18@181258 by Joris van den Heuvel

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Check out FRAM. It's non-volatile RAM without any energy source. Sort of
like EEPROM but without the write delay. There are versions that are pin
compatible with an 62256. I'm about to experiment with their serial 8Kx8
chip.

Joris.

{Original Message removed}

2001\10\18@183422 by Douglas Wood

picon face
>> My microcontroller circuit has a 62256 (32Kx8) RAM chip, which is used
for
>> storing some important data I want to retain even when the power is off.
>> What is the normal way to retain data on RAM? Is using a battery the best
>> solution? If so, how do I turn on the battery "only" when the power is
off?

Try using one of the FRAM devices from RAMTRON. They communicate in the same
way as EEPROM devices, but without the write cycle delays.

Douglas Wood
Software Engineer
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2001\10\18@194806 by Byron A Jeff

face picon face
On Thu, Oct 18, 2001 at 02:19:57PM -0500, Matt Pobursky wrote:
> On Thu, 18 Oct 2001 14:04:01 -0400, Byron A Jeff wrote:
> >
> >This discussion seems to be going on in 3 or 4 threads at the
> >same time.
> >I posted the same basic question but got no responses.
> >
> >Here's my question: Why not skip the RAM supervisor, and simply
> >power the
> >PIC along with the RAM? Put the PIC into sleep after it
> >completes a read or
> >write, with the CE held high. Then you have no write corruption,
> >the PIC
> >continues to be powered for the duration, and is only draws
> >microamps in
> >sleep mode.
>
> It should work. I just checked a Samsung SRAM datasheet and it
> says as long as CS1* > Vcc-0.2V, CS2 > Vcc-0.2V or CS2 < 0.2V,
> Other inputs=0~Vcc, then you will be in low power standby.

That was my read also.

{Quote hidden}

So are you suggesting retaining power on the latches? Or is that microamp
draw from some phantom power source when Vcc is removed from the latches?
Also the address latches can be three stated. I was planning on using
74HC[T]259 bit addressible latches for the control, But if three stating
is critical for low current I could simply throw more 74HC[T]573's at the
job and disable the outputs for all the latches in standby mode.


> The only thing to watch for is leakage currents in/out of the
> SRAM address and data pins. The data pics of the SRAM will be
> Hi-z so I don't think they'll be a problem. I'm not sure what the
> address lines look like, but I'm guessing they look like Hi-z
> CMOS inputs. You should be able to use a PIC port pin as a
> tri-state signal when you "go to sleep".

I'm almost clear except on whether or not to power down the latches. A brief
review of the latch datasheet indicates that the leakage current is in the
nanoamp range when quiescent.

>
> Signals between your PIC and the buffer/latch inputs should be
> only CMOS level leakages (very low microamps) when not switching
> also.

Latch on? Latch off? ;-)

>
> >The task here is on my short list. Looking forward to some more
> >discussion
> >on the subject.
>
> I think it should work fine. Keep us posted, I'm interested what
> you come up with.

Well I'm just trying to keep it simple. We all know that a sleeping PIC has
very little current draw. We know that's also the same for the RAM. The latches
are the only question. I've decided that my first design will power the
latches. I'm really planning on having a lot a juice available in the form of
3 AAA nicads. This gives me a nominal 3.6V of backup with 220 mAh of power.
With the nominal current draw of under 100 uA it should retain backup upwards
of 90 days.

BTW what's the usual way of measuring such small currents? Can it be done with
a normal DMM?

Thanks for the info.

BAJ

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2001\10\19@053827 by asena

picon face
> > Why dont you use a FRAM ?
> >
> > They're very nice NVRAM, that write at the same speed as the bus.
>
> Be aware that FRAM wears on reads in addition to writes. And while the number
> of accesses can be quite high, it is finite.
>
> The other issues are always cost, availablility, and product lifetime in terms
> of manufacturers keeping a part available.
>
> Personally I'd go with the EEPROM unless write speed/endurance were a
> significant issue.
>
> BAJ


Yes, i agree.
Though i think probably speed is a concern, Thats why i mentioned FRAM for the job.

Sena



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2001\10\19@161413 by Peter L. Peres

picon face
> Be aware that FRAM wears on reads in addition to writes. And while the
> number of accesses can be quite high, it is finite.

Is there some valid explanation for this ? I have never heard of core
memory being 'worn out' before.

A nice learning PIC project idea imho: build a 16 bit non-volatile memory
using a 16F84 and 16 saturable cores in a 4x4 matrix on portb with a sense
wire on a pin on porta using a single window comparator... Saturable cores
can be made by using steel washers from the hardware store in a pinch <g>.
They should need no more than 3 turns each assuming capacitor discharge
scan pulsing.

On another line, is there anything like hall or mr-read saturable magnetic
material memory in use ? I mean like core memory, but with readout using
mr or hall elements instead of delete pulse sensing like in a proper core
memory.

Peter

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2001\10\19@162823 by Peter L. Peres

picon face
> The cheapest way to turn on the battery when the power is off is to
> use a diode. Also a small pnp + 3 resistors current charge is required
> when accu is used. I think you can't find a chip less expensive than
> all this devices. Vasile

Actually you normally need two diodes, one from supply and one from the
backup battery, to ram +vdd, and a pullup of 1M or so between ram +vdd and
/ce to keep it disabled. A tiny twin diode in SOT23 and 1M pullup will
work fine. Decouple the ram directly at its pins after the diodes with
0.1uF ceramic + 4.7uF tantalum, or as per manufacturer's data sheet.

It is also necessary that the unpowered circuitry connected to /ce does
not pull it low. One way is, to use a heftier pullup and a NPN transistor
as 'fake' TTL input stage (E to driver, B to weak divider holding 1.8V
when the base is not driven, and C to ram /ce). This circuit relies on the
base being drawn to gnd when the external circuit is not powered (and thus
the divider also not). Do not decouple the base divider with a capacitor.
Another is to use a single 4S66F CMOS gate as separator on the /ce line
with the enable wired to the reset or brownout sensor on the main powered
circuit. Yet another is to use the /ce line hard-wired to a reset or power
sense circuit that provides disable when the voltage goes away. Tieing it
to a known good CPU monitor's output /reset line is a good way to avoid
data corruption on turn on and turn off.

There are specific chips that provide standby power, plus input/stadby
switching, plus low battery sensing etc, like the Seiko S8230 and S8232
for exmaple. They also have a suitable /CE and reset driver built-in, plus
a regulator for Vsby when it is provided from external power. Maybe you
should look at these.

I once made a DS1230Y replacement by gluing these parts and a small
diameter (smaller than the 300mil wide 6116 body) lithium coin cell
directly on the back of a 6116 SRAM. The /ce pin was cut off short and its
remainder glued on below it with epoxy (with no electrical contact).
Worked perfectly. Data retention was well over 1 year with a homemade
design and can be >10 years with an industrial one.

hope this helps,

Peter

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2001\10\19@172104 by Byron A Jeff

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On Fri, Oct 19, 2001 at 09:59:21PM +0200, Peter L. Peres wrote:
> > Be aware that FRAM wears on reads in addition to writes. And while the
> > number of accesses can be quite high, it is finite.
>
> Is there some valid explanation for this ? I have never heard of core
> memory being 'worn out' before.

There's a bit of explanation on Fujitsu's FRAM endurance page:

http://edevice.fujitsu.com/fj/CATALOG/AD00/00-00015/1e-5.html

BAJ

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2001\10\20@072808 by Peter L. Peres

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> There's a bit of explanation on Fujitsu's FRAM endurance page:
>
> http://edevice.fujitsu.com/fj/CATALOG/AD00/00-00015/1e-5.html
>
> BAJ

Thanks for the excellent link,

Peter

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