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'[EE]: Help troubleshooting a JFET circuit.'
2017\09\11@084137 by James Burkart

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Hello all!

I am working on a lab for a class and we are given a simple self-biased
N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
+15V.

Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.

Assuming only one component can be bad, what is the likely problem?

I built the circuit in MPLab and tried everything I could think of to
recreate the voltages, but everything I tried does not work. Shorting Rd
was my first thought, but that also results in Vds being 12.6V. What am I
missing? Can anyone get me on the right track? I have shorted and opened
all resistors, the only thing I can't do (or don't know how to do) is
recreate a faulty FET.

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Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
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2017\09\11@085728 by James Burkart

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I don't know why I said MPLab, I meant MultiSim.

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Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
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On Mon, Sep 11, 2017 at 6:40 AM, James Burkart <spam_OUTjamesTakeThisOuTspamburkartstudios.com>
wrote:

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2017\09\11@112637 by George Smith

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James Burkart wrote:

> I am working on a lab for a class and we are given a simple self-biased
> N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> +15V.
>
> Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
>
> Assuming only one component can be bad, what is the likely problem?
> What do you get if Rd goes open circuit and you measure the voltages with an AVO8? :-)

George Smith
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2017\09\11@113149 by George Smith

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George Smith wrote:
Duh! - I meant Rs!

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2017\09\11@125737 by Dwayne Reid

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Hi there.

Consider what happens if Rs goes open.  Also consider that the gate junction becomes forward-biased when Vgs goes negative.

dwayne


At 06:40 AM 9/11/2017, James Burkart wrote:
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2017\09\11@135818 by Sean Breheny

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I might be missing something but I don't think this problem is well
designed. I think we can narrow it down to Rs being open but technically it
isn't possible, as far as I can see, to get exactly the voltages mentioned.
Vd=15V implies that absolutely no current is flowing from the supply, so
there shouldn't be ANY voltage drop across the drain-source connection.

Here's my train of thought:

If Rd were open, Vd would be zero.
If Rd were shorted, the current would be limited by the negative Vgs which
would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
the gate junction for an N JFET), so there would be some Vds drop of
several volts.

If Rg were open, I think the FET behavior would tend toward the Vgs=0
behavior where almost the maximum current flows, but then Vd would be less
than 15V.

If Rg were shorted, the circuit would behave almost as if nothing were
wrong, unless 15V was enough to cause reverse breakdown of the gate
junction, but in that case Vd would be less than 15V since an excessive
leakage current would flow.

If Rs were shorted, Vs would be zero.
If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
to what we observe. In the real world, the 10Meg input impedance of a
typical multimeter would probably produce something similar to what is
claimed here (it would act as a very high value of Vs) but Vd would not be
identically 15V.


On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <dwaynerspamKILLspamplanet.eon.net>
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2017\09\11@140647 by Sean Breheny

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I forgot the bad FET possibility. I still think we can rule it out:

If D-S is shorted, then Vd would be less than 15V
If D-S is open, Vs would be zero.
If G-channel is open, current would flow and Vd would be less than 15V.
If the G-channel junction is shorted, current would flow and Vd would be
less than 15V.


On Mon, Sep 11, 2017 at 1:58 PM, Sean Breheny <EraseMEshb7spam_OUTspamTakeThisOuTcornell.edu> wrote:

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2017\09\11@151004 by Dwayne Reid

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Hi there, Sean.

You are forgetting about current that flows through the gate resistor to Ground.  This is a J-FET, so the gate diode junction is forward biased if Rs is open.

Another possibility that Rs is very high value.  I haven't bothered to work out the math for the possible high value.

dwayne


At 11:58 AM 9/11/2017, Sean Breheny wrote:
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Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
http://www.trinity-electronics.com
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2017\09\11@154403 by Sean Breheny

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Dwane - no, for an n jfet the gate would only be forward biased if it were
higher than the source in voltage (gate more positive than source). Jfets
are always depletion mode devices so they are on with no gate bias and turn
off when reverse bias is applied to the gate-channel junction


On Sep 11, 2017 3:10 PM, "Dwayne Reid" <spamBeGonedwaynerspamBeGonespamplanet.eon.net> wrote:

Hi there, Sean.

You are forgetting about current that flows through the gate resistor
to Ground.  This is a J-FET, so the gate diode junction is forward
biased if Rs is open.

Another possibility that Rs is very high value.  I haven't bothered
to work out the math for the possible high value.

dwayne


At 11:58 AM 9/11/2017, Sean Breheny wrote:
{Quote hidden}

Rd
> > >was my first thought, but that also results in Vds being 12.6V. What
am I
> > >missing? Can anyone get me on the right track? I have shorted and
opened
{Quote hidden}

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Dwayne Reid   <RemoveMEdwaynerspamTakeThisOuTplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

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2017\09\11@163254 by Sean Breheny

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Dwayne - sorry for mis-spelling your name.
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2017\09\11@204503 by James Burkart

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That was my second guess. Eliminating Rs reverse biases the FET at about
-5V, and Vds is 10V.

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Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
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On Mon, Sep 11, 2017 at 9:26 AM, George Smith <emcq-jrcrEraseMEspam.....dea.spamcon.org>
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2017\09\11@210332 by James Burkart

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Raising the value of Rs serves to increase negative biasing the gate, which
raises the value of Vds. Lowering it brings Vg closer to 0V, but increases
Id, and increases the voltage drop across Rd.

Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this case
I do get 15V at Vd since there is virtually no current through the
transistor (spice simulation shows 177pA) but then Vds becomes ~10V.

--
Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
*Facebook:* facebook.com/burkartstudios

On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <EraseMEdwaynerspamplanet.eon.net> wrote:

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2017\09\11@210455 by James Burkart

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Actually I meant Vgs closer to 0V, not Vg.

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James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
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On Mon, Sep 11, 2017 at 7:02 PM, James Burkart <RemoveMEjamesTakeThisOuTspamspamburkartstudios.com>
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2017\09\11@223133 by Sean Breheny

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Could you post a photo of the original problem so we could see if somehow
you are interpreting it differently than we would?

I just tried the physical circuit (I used a J310 because I don't have a
2N4860 and J310 seems very similar) and I can't get anything like the
voltages they describe by making any one resistor open or shorted,
regardless of whether I use a 10Mohm input impedance voltmeter or a 10G ohm
impedance voltmeter. If I open the source resistor and measure Vs, I get
about 3V with either the Rin=10Mohm meter or the Rin=10Gohm meter.


On Mon, Sep 11, 2017 at 9:04 PM, James Burkart <spamBeGonejamesSTOPspamspamEraseMEburkartstudios.com>
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2017\09\11@223753 by James Burkart

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Sure thing!

I saved the lab to a word doc and put it on my Google Drive.
https://drive.google.com/file/d/0Bw1n2tiO8ikQVzlaekYyblVYaXM/view?usp=sharing

--
Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
*Facebook:* facebook.com/burkartstudios

On Mon, Sep 11, 2017 at 8:31 PM, Sean Breheny <.....shb7spam_OUTspamcornell.edu> wrote:

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2017\09\11@224147 by James Burkart

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The closest I can get is shorting the gate to Vdd, however there is still
some voltage drop across Rd, and in the real world that would fry the gate
to channel junction.

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James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
*Facebook:* facebook.com/burkartstudios

On Mon, Sep 11, 2017 at 8:37 PM, James Burkart <TakeThisOuTjamesspamspamburkartstudios.com>
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2017\09\11@224437 by Sean Breheny

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Hmmm - it is as I had envisioned it so there is no major revelation.

For cases 1 and 3, did you get that R3 (Rs) is shorted for #1 and for #3
that the JFET is bad (D-S open)?

On Mon, Sep 11, 2017 at 10:37 PM, James Burkart <jamesspamBeGonespamburkartstudios.com>
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2017\09\11@230850 by James Burkart

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Yup, that's what I got for 1 and 3. I think there was a mistake made when
the lab was written. I've come across problems like this in many classes at
this school, Grantham, as well as at DeVry. If it was a simple mistake,
fine. But the problem is that these questions in most cases were written
years ago, and either students have been answering them "wrong" all these
years, or the error has been brought to an instructor's attention, but
nothing is ever done about it. So very frustrating.

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Sincerely,

James Burkart
*Filmmaker & Documentarian*

*Burkart Studios*
925.667.7175 | Personal
415.738.2071 | Office

*Web:* burkartstudios.com
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On Mon, Sep 11, 2017 at 8:44 PM, Sean Breheny <RemoveMEshb7@spam@spamspamBeGonecornell.edu> wrote:

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2017\09\12@125949 by Dwayne Reid

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Hi there, Sean.

You are right - for some reason, I was thinking P-channel.  Which, of course, is completely erroneous.

Call it a brain fart!

dwayne


At 01:43 PM 9/11/2017, Sean Breheny wrote:
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-- Dwayne Reid   <RemoveMEdwaynerspamspamBeGoneplanet.eon.net>
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http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

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