> Hello all!
>
> I am working on a lab for a class and we are given a simple self-biased
> N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> +15V.
>
> Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
>
> Assuming only one component can be bad, what is the likely problem?
>
> I built the circuit in MPLab and tried everything I could think of to
> recreate the voltages, but everything I tried does not work. Shorting Rd
> was my first thought, but that also results in Vds being 12.6V. What am I
> missing? Can anyone get me on the right track? I have shorted and opened
> all resistors, the only thing I can't do (or don't know how to do) is
> recreate a faulty FET.
>
> --
> Sincerely,
>
> James Burkart
> *Filmmaker & Documentarian*
>
> *Burkart Studios*
> 925.667.7175 <(925)%20667-7175> | Personal
> 415.738.2071 <(415)%20738-2071> | Office
>
> *Web:* burkartstudios.com
> *Facebook:* facebook.com/burkartstudios
>

>Hello all!
>
>I am working on a lab for a class and we are given a simple self-biased
>N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
>+15V.
>
>Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
>
>Assuming only one component can be bad, what is the likely problem?
>
>I built the circuit in MPLab and tried everything I could think of to
>recreate the voltages, but everything I tried does not work. Shorting Rd
>was my first thought, but that also results in Vds being 12.6V. What am I
>missing? Can anyone get me on the right track? I have shorted and opened
>all resistors, the only thing I can't do (or don't know how to do) is
>recreate a faulty FET.
>
>--
>Sincerely,
>
>James Burkart
>*Filmmaker & Documentarian*
>
>*Burkart Studios*
>925.667.7175 | Personal
>415.738.2071 | Office
>
>*Web:* burkartstudios.com
>*Facebook:* facebook.com/burkartstudios
>--
>http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

> Hi there.
>
> Consider what happens if Rs goes open.  Also consider that the gate
> junction becomes forward-biased when Vgs goes negative.
>
> dwayne
>
>
> At 06:40 AM 9/11/2017, James Burkart wrote:
> >Hello all!
> >
> >I am working on a lab for a class and we are given a simple self-biased
> >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> >+15V.
> >
> >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V..
> >
> >Assuming only one component can be bad, what is the likely problem?
> >
> >I built the circuit in MPLab and tried everything I could think of to
> >recreate the voltages, but everything I tried does not work. Shorting Rd
> >was my first thought, but that also results in Vds being 12.6V. What am I
> >missing? Can anyone get me on the right track? I have shorted and opened
> >all resistors, the only thing I can't do (or don't know how to do) is
> >recreate a faulty FET.
> >
> >--
> >Sincerely,
> >
> >James Burkart
> >*Filmmaker & Documentarian*
> >
> >*Burkart Studios*
> >925.667.7175 | Personal
> >415.738.2071 | Office
> >
> >*Web:* burkartstudios.com
> >*Facebook:* facebook.com/burkartstudios
> >--
> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >View/change your membership options at
> >http://mailman.mit.edu/mailman/listinfo/piclist
>
>
> --
> Dwayne Reid   <.....dwaynerKILLspam.....planet.eon.net>
> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
> http://www.trinity-electronics.com
> Custom Electronics Design and Manufacturing
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

> I might be missing something but I don't think this problem is well
> designed. I think we can narrow it down to Rs being open but technically it
> isn't possible, as far as I can see, to get exactly the voltages mentioned.
> Vd=15V implies that absolutely no current is flowing from the supply, so
> there shouldn't be ANY voltage drop across the drain-source connection.
>
> Here's my train of thought:
>
> If Rd were open, Vd would be zero.
> If Rd were shorted, the current would be limited by the negative Vgs which
> would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
> the gate junction for an N JFET), so there would be some Vds drop of
> several volts.
>
> If Rg were open, I think the FET behavior would tend toward the Vgs=0
> behavior where almost the maximum current flows, but then Vd would be less
> than 15V.
>
> If Rg were shorted, the circuit would behave almost as if nothing were
> wrong, unless 15V was enough to cause reverse breakdown of the gate
> junction, but in that case Vd would be less than 15V since an excessive
> leakage current would flow.
>
> If Rs were shorted, Vs would be zero.
> If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
> to what we observe. In the real world, the 10Meg input impedance of a
> typical multimeter would probably produce something similar to what is
> claimed here (it would act as a very high value of Vs) but Vd would not be
> identically 15V.
>
>
> On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <dwaynerspam_OUTplanet.eon.net>
> wrote:
>
>> Hi there.
>>
>> Consider what happens if Rs goes open.  Also consider that the gate
>> junction becomes forward-biased when Vgs goes negative.
>>
>> dwayne
>>
>>
>> At 06:40 AM 9/11/2017, James Burkart wrote:
>> >Hello all!
>> >
>> >I am working on a lab for a class and we are given a simple self-biased
>> >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
>> >+15V.
>> >
>> >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
>> >
>> >Assuming only one component can be bad, what is the likely problem?
>> >
>> >I built the circuit in MPLab and tried everything I could think of to
>> >recreate the voltages, but everything I tried does not work. Shorting Rd
>> >was my first thought, but that also results in Vds being 12.6V. What am I
>> >missing? Can anyone get me on the right track? I have shorted and opened
>> >all resistors, the only thing I can't do (or don't know how to do) is
>> >recreate a faulty FET.
>> >
>> >--
>> >Sincerely,
>> >
>> >James Burkart
>> >*Filmmaker & Documentarian*
>> >
>> >*Burkart Studios*
>> >925.667.7175 | Personal
>> >415.738.2071 | Office
>> >
>> >*Web:* burkartstudios.com
>> >*Facebook:* facebook.com/burkartstudios
>> >--
>> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> >View/change your membership options at
>> >mailman.mit.edu/mailman/listinfo/piclist
>>
>>
>> --
>> Dwayne Reid   <@spam@dwaynerKILLspamplanet.eon.net>
>> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
>> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
>> http://www.trinity-electronics.com
>> Custom Electronics Design and Manufacturing
>>
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> mailman.mit.edu/mailman/listinfo/piclist
>>
>
>

>I might be missing something but I don't think this problem is well
>designed. I think we can narrow it down to Rs being open but technically it
>isn't possible, as far as I can see, to get exactly the voltages mentioned..
>Vd=15V implies that absolutely no current is flowing from the supply, so
>there shouldn't be ANY voltage drop across the drain-source connection.
>
>Here's my train of thought:
>
>If Rd were open, Vd would be zero.
>If Rd were shorted, the current would be limited by the negative Vgs which
>would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
>the gate junction for an N JFET), so there would be some Vds drop of
>several volts.
>
>If Rg were open, I think the FET behavior would tend toward the Vgs=0
>behavior where almost the maximum current flows, but then Vd would be less
>than 15V.
>
>If Rg were shorted, the circuit would behave almost as if nothing were
>wrong, unless 15V was enough to cause reverse breakdown of the gate
>junction, but in that case Vd would be less than 15V since an excessive
>leakage current would flow.
>
>If Rs were shorted, Vs would be zero.
>If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
>to what we observe. In the real world, the 10Meg input impedance of a
>typical multimeter would probably produce something similar to what is
>claimed here (it would act as a very high value of Vs) but Vd would not be
>identically 15V.
>
>
>On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <KILLspamdwaynerKILLspamplanet.eon.net>
>wrote:
>
> > Hi there.
> >
> > Consider what happens if Rs goes open.  Also consider that the gate
> > junction becomes forward-biased when Vgs goes negative.
> >
> > dwayne
> >
> >
> > At 06:40 AM 9/11/2017, James Burkart wrote:
> > >Hello all!
> > >
> > >I am working on a lab for a class and we are given a simple self-biased
> > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> > >+15V.
> > >
> > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> > >
> > >Assuming only one component can be bad, what is the likely problem?
> > >
> > >I built the circuit in MPLab and tried everything I could think of to
> > >recreate the voltages, but everything I tried does not work. Shorting Rd
> > >was my first thought, but that also results in Vds being 12.6V. What am I
> > >missing? Can anyone get me on the right track? I have shorted and opened
> > >all resistors, the only thing I can't do (or don't know how to do) is
> > >recreate a faulty FET.
> > >
> > >--
> > >Sincerely,
> > >
> > >James Burkart
> > >*Filmmaker & Documentarian*
> > >
> > >*Burkart Studios*
> > >925.667.7175 | Personal
> > >415.738.2071 | Office
> > >
> > >*Web:* burkartstudios.com
> > >*Facebook:* facebook.com/burkartstudios

>I might be missing something but I don't think this problem is well
>designed. I think we can narrow it down to Rs being open but technically it
>isn't possible, as far as I can see, to get exactly the voltages mentioned..
>Vd=15V implies that absolutely no current is flowing from the supply, so
>there shouldn't be ANY voltage drop across the drain-source connection.
>
>Here's my train of thought:
>
>If Rd were open, Vd would be zero.
>If Rd were shorted, the current would be limited by the negative Vgs which
>would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
>the gate junction for an N JFET), so there would be some Vds drop of
>several volts.
>
>If Rg were open, I think the FET behavior would tend toward the Vgs=0
>behavior where almost the maximum current flows, but then Vd would be less
>than 15V.
>
>If Rg were shorted, the circuit would behave almost as if nothing were
>wrong, unless 15V was enough to cause reverse breakdown of the gate
>junction, but in that case Vd would be less than 15V since an excessive
>leakage current would flow.
>
>If Rs were shorted, Vs would be zero.
>If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
>to what we observe. In the real world, the 10Meg input impedance of a
>typical multimeter would probably produce something similar to what is
>claimed here (it would act as a very high value of Vs) but Vd would not be
>identically 15V.
>
>
>On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <TakeThisOuTdwaynerEraseMEspam_OUTplanet.eon.net>
>wrote:
>
> > Hi there.
> >
> > Consider what happens if Rs goes open.  Also consider that the gate
> > junction becomes forward-biased when Vgs goes negative.
> >
> > dwayne
> >
> >
> > At 06:40 AM 9/11/2017, James Burkart wrote:
> > >Hello all!
> > >
> > >I am working on a lab for a class and we are given a simple self-biased
> > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> > >+15V.
> > >
> > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> > >
> > >Assuming only one component can be bad, what is the likely problem?
> > >
> > >I built the circuit in MPLab and tried everything I could think of to
> > >recreate the voltages, but everything I tried does not work. Shorting

> > >all resistors, the only thing I can't do (or don't know how to do) is
> > >recreate a faulty FET.
> > >
> > >--
> > >Sincerely,
> > >
> > >James Burkart
> > >*Filmmaker & Documentarian*
> > >
> > >*Burkart Studios*
> > >925.667.7175 | Personal
> > >415.738.2071 | Office
> > >
> > >*Web:* burkartstudios.com
> > >*Facebook:* facebook.com/burkartstudios

> James Burkart wrote:
>
> > I am working on a lab for a class and we are given a simple self-biased
> > N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> > +15V.
> >
> > Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> >
> > Assuming only one component can be bad, what is the likely problem?
> >
> What do you get if Rd goes open circuit and you measure the voltages
> with an AVO8? :-)
>
> George Smith
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

> Hi there, Sean.
>
> You are forgetting about current that flows through the gate resistor
> to Ground.  This is a J-FET, so the gate diode junction is forward
> biased if Rs is open.
>
> Another possibility that Rs is very high value.  I haven't bothered
> to work out the math for the possible high value.
>
> dwayne
>
>
> At 11:58 AM 9/11/2017, Sean Breheny wrote:
> >I might be missing something but I don't think this problem is well
> >designed. I think we can narrow it down to Rs being open but technically
> it
> >isn't possible, as far as I can see, to get exactly the voltages
> mentioned.
> >Vd=15V implies that absolutely no current is flowing from the supply, so
> >there shouldn't be ANY voltage drop across the drain-source connection.
> >
> >Here's my train of thought:
> >
> >If Rd were open, Vd would be zero.
> >If Rd were shorted, the current would be limited by the negative Vgs which
> >would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
> >the gate junction for an N JFET), so there would be some Vds drop of
> >several volts.
> >
> >If Rg were open, I think the FET behavior would tend toward the Vgs=0
> >behavior where almost the maximum current flows, but then Vd would be less
> >than 15V.
> >
> >If Rg were shorted, the circuit would behave almost as if nothing were
> >wrong, unless 15V was enough to cause reverse breakdown of the gate
> >junction, but in that case Vd would be less than 15V since an excessive
> >leakage current would flow.
> >
> >If Rs were shorted, Vs would be zero.
> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
> >to what we observe. In the real world, the 10Meg input impedance of a
> >typical multimeter would probably produce something similar to what is
> >claimed here (it would act as a very high value of Vs) but Vd would not be
> >identically 15V.
> >
> >
> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <RemoveMEdwaynerEraseMEEraseMEplanet.eon.net>
> >wrote:
> >
> > > Hi there.
> > >
> > > Consider what happens if Rs goes open.  Also consider that the gate
> > > junction becomes forward-biased when Vgs goes negative.
> > >
> > > dwayne
> > >
> > >
> > > At 06:40 AM 9/11/2017, James Burkart wrote:
> > > >Hello all!
> > > >
> > > >I am working on a lab for a class and we are given a simple
> self-biased
> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd
> =
> > > >+15V.
> > > >
> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> > > >
> > > >Assuming only one component can be bad, what is the likely problem?
> > > >
> > > >I built the circuit in MPLab and tried everything I could think of to
> > > >recreate the voltages, but everything I tried does not work. Shorting
> Rd
> > > >was my first thought, but that also results in Vds being 12.6V. What
> am I
> > > >missing? Can anyone get me on the right track? I have shorted and
> opened
> > > >all resistors, the only thing I can't do (or don't know how to do) is
> > > >recreate a faulty FET.
> > > >
> > > >--
> > > >Sincerely,
> > > >
> > > >James Burkart
> > > >*Filmmaker & Documentarian*
> > > >
> > > >*Burkart Studios*
> > > >925.667.7175 | Personal
> > > >415.738.2071 | Office
> > > >
> > > >*Web:* burkartstudios.com
> > > >*Facebook:* facebook.com/burkartstudios
>
>
> --
> Dwayne Reid   <RemoveMEdwaynerspam_OUTKILLspamplanet.eon.net>
> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
> http://www.trinity-electronics.com
> Custom Electronics Design and Manufacturing
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

> Raising the value of Rs serves to increase negative biasing the gate,
> which raises the value of Vds. Lowering it brings Vg closer to 0V, but
> increases Id, and increases the voltage drop across Rd.
>
> Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this case
> I do get 15V at Vd since there is virtually no current through the
> transistor (spice simulation shows 177pA) but then Vds becomes ~10V.
>
> --
> Sincerely,
>
> James Burkart
> *Filmmaker & Documentarian*
>
> *Burkart Studios*
> 925.667.7175 <(925)%20667-7175> | Personal
> 415.738.2071 <(415)%20738-2071> | Office
>
> *Web:* burkartstudios.com
> *Facebook:* facebook.com/burkartstudios
>
> On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <EraseMEdwaynerspamspamBeGoneplanet.eon.net>
> wrote:
>
>> Hi there, Sean.
>>
>> You are forgetting about current that flows through the gate resistor
>> to Ground.  This is a J-FET, so the gate diode junction is forward
>> biased if Rs is open.
>>
>> Another possibility that Rs is very high value.  I haven't bothered
>> to work out the math for the possible high value.
>>
>> dwayne
>>
>>
>> At 11:58 AM 9/11/2017, Sean Breheny wrote:
>> >I might be missing something but I don't think this problem is well
>> >designed. I think we can narrow it down to Rs being open but technically
>> it
>> >isn't possible, as far as I can see, to get exactly the voltages
>> mentioned.
>> >Vd=15V implies that absolutely no current is flowing from the supply, so
>> >there shouldn't be ANY voltage drop across the drain-source connection.
>> >
>> >Here's my train of thought:
>> >
>> >If Rd were open, Vd would be zero.
>> >If Rd were shorted, the current would be limited by the negative Vgs
>> which
>> >would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
>> >the gate junction for an N JFET), so there would be some Vds drop of
>> >several volts.
>> >
>> >If Rg were open, I think the FET behavior would tend toward the Vgs=0
>> >behavior where almost the maximum current flows, but then Vd would be
>> less
>> >than 15V.
>> >
>> >If Rg were shorted, the circuit would behave almost as if nothing were
>> >wrong, unless 15V was enough to cause reverse breakdown of the gate
>> >junction, but in that case Vd would be less than 15V since an excessive
>> >leakage current would flow.
>> >
>> >If Rs were shorted, Vs would be zero.
>> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
>> >to what we observe. In the real world, the 10Meg input impedance of a
>> >typical multimeter would probably produce something similar to what is
>> >claimed here (it would act as a very high value of Vs) but Vd would not
>> be
>> >identically 15V.
>> >
>> >
>> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <RemoveMEdwaynerKILLspamplanet.eon.net>
>> >wrote:
>> >
>> > > Hi there.
>> > >
>> > > Consider what happens if Rs goes open.  Also consider that the gate
>> > > junction becomes forward-biased when Vgs goes negative.
>> > >
>> > > dwayne
>> > >
>> > >
>> > > At 06:40 AM 9/11/2017, James Burkart wrote:
>> > > >Hello all!
>> > > >
>> > > >I am working on a lab for a class and we are given a simple
>> self-biased
>> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860,
>> Vdd =
>> > > >+15V.
>> > > >
>> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
>> > > >
>> > > >Assuming only one component can be bad, what is the likely problem?
>> > > >
>> > > >I built the circuit in MPLab and tried everything I could think of to
>> > > >recreate the voltages, but everything I tried does not work.
>> Shorting Rd
>> > > >was my first thought, but that also results in Vds being 12.6V. What
>> am I
>> > > >missing? Can anyone get me on the right track? I have shorted and
>> opened
>> > > >all resistors, the only thing I can't do (or don't know how to do) is
>> > > >recreate a faulty FET.
>> > > >
>> > > >--
>> > > >Sincerely,
>> > > >
>> > > >James Burkart
>> > > >*Filmmaker & Documentarian*
>> > > >
>> > > >*Burkart Studios*
>> > > >925.667.7175 <(925)%20667-7175> | Personal
>> > > >415.738.2071 <(415)%20738-2071> | Office
>> > > >
>> > > >*Web:* burkartstudios.com
>> > > >*Facebook:* facebook.com/burkartstudios
>>
>>
>> --
>> Dwayne Reid   <dwaynerSTOPspamspam_OUTplanet.eon.net>
>> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
>> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
>> http://www.trinity-electronics.com
>> Custom Electronics Design and Manufacturing
>>
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> mailman.mit.edu/mailman/listinfo/piclist
>>
>
>

> Actually I meant Vgs closer to 0V, not Vg.
>
> --
> Sincerely,
>
> James Burkart
> *Filmmaker & Documentarian*
>
> *Burkart Studios*
> 925.667.7175 | Personal
> 415.738.2071 | Office
>
> *Web:* burkartstudios.com
> *Facebook:* facebook.com/burkartstudios
>
> On Mon, Sep 11, 2017 at 7:02 PM, James Burkart <KILLspamjamesspamBeGoneburkartstudios.com>
> wrote:
>
> > Raising the value of Rs serves to increase negative biasing the gate,
> > which raises the value of Vds. Lowering it brings Vg closer to 0V, but
> > increases Id, and increases the voltage drop across Rd.
> >
> > Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this
> case
> > I do get 15V at Vd since there is virtually no current through the
> > transistor (spice simulation shows 177pA) but then Vds becomes ~10V.
> >
> > --
> > Sincerely,
> >
> > James Burkart
> > *Filmmaker & Documentarian*
> >
> > *Burkart Studios*
> > 925.667.7175 <(925)%20667-7175> | Personal
> > 415.738.2071 <(415)%20738-2071> | Office
> >
> > *Web:* burkartstudios.com
> > *Facebook:* facebook.com/burkartstudios
> >
> > On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <EraseMEdwaynerEraseMEplanet.eon.net>
> > wrote:
> >
> >> Hi there, Sean.
> >>
> >> You are forgetting about current that flows through the gate resistor
> >> to Ground.  This is a J-FET, so the gate diode junction is forward
> >> biased if Rs is open.
> >>
> >> Another possibility that Rs is very high value.  I haven't bothered
> >> to work out the math for the possible high value.
> >>
> >> dwayne
> >>
> >>
> >> At 11:58 AM 9/11/2017, Sean Breheny wrote:
> >> >I might be missing something but I don't think this problem is well
> >> >designed. I think we can narrow it down to Rs being open but
> technically
> >> it
> >> >isn't possible, as far as I can see, to get exactly the voltages
> >> mentioned.
> >> >Vd=15V implies that absolutely no current is flowing from the supply,
> so
> >> >there shouldn't be ANY voltage drop across the drain-source connection.
> >> >
> >> >Here's my train of thought:
> >> >
> >> >If Rd were open, Vd would be zero.
> >> >If Rd were shorted, the current would be limited by the negative Vgs
> >> which
> >> >would develop (I am defining negative Vgs as Vs>Vg, which reverse
> biases
> >> >the gate junction for an N JFET), so there would be some Vds drop of
> >> >several volts.
> >> >
> >> >If Rg were open, I think the FET behavior would tend toward the Vgs=0
> >> >behavior where almost the maximum current flows, but then Vd would be
> >> less
> >> >than 15V.
> >> >
> >> >If Rg were shorted, the circuit would behave almost as if nothing were
> >> >wrong, unless 15V was enough to cause reverse breakdown of the gate
> >> >junction, but in that case Vd would be less than 15V since an excessive
> >> >leakage current would flow.
> >> >
> >> >If Rs were shorted, Vs would be zero.
> >> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the
> closest
> >> >to what we observe. In the real world, the 10Meg input impedance of a
> >> >typical multimeter would probably produce something similar to what is
> >> >claimed here (it would act as a very high value of Vs) but Vd would not
> >> be
> >> >identically 15V.
> >> >
> >> >
> >> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <@spam@dwayner@spam@spam_OUTplanet.eon.net>
> >> >wrote:
> >> >
> >> > > Hi there.
> >> > >
> >> > > Consider what happens if Rs goes open.  Also consider that the gate
> >> > > junction becomes forward-biased when Vgs goes negative.
> >> > >
> >> > > dwayne
> >> > >
> >> > >
> >> > > At 06:40 AM 9/11/2017, James Burkart wrote:
> >> > > >Hello all!
> >> > > >
> >> > > >I am working on a lab for a class and we are given a simple
> >> self-biased
> >> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860,
> >> Vdd =
> >> > > >+15V.
> >> > > >
> >> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> >> > > >
> >> > > >Assuming only one component can be bad, what is the likely problem?
> >> > > >
> >> > > >I built the circuit in MPLab and tried everything I could think of
> to
> >> > > >recreate the voltages, but everything I tried does not work.
> >> Shorting Rd
> >> > > >was my first thought, but that also results in Vds being 12.6V.
> What
> >> am I
> >> > > >missing? Can anyone get me on the right track? I have shorted and
> >> opened
> >> > > >all resistors, the only thing I can't do (or don't know how to do)
> is
> >> > > >recreate a faulty FET.
> >> > > >
> >> > > >--
> >> > > >Sincerely,
> >> > > >
> >> > > >James Burkart
> >> > > >*Filmmaker & Documentarian*
> >> > > >
> >> > > >*Burkart Studios*
> >> > > >925.667.7175 <(925)%20667-7175> | Personal
> >> > > >415.738.2071 <(415)%20738-2071> | Office
> >> > > >
> >> > > >*Web:* burkartstudios.com
> >> > > >*Facebook:* facebook.com/burkartstudios
> >>
> >>
> >> --
> >> Dwayne Reid   <spamBeGonedwaynerKILLspamplanet.eon.net>
> >> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
> >> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
> >> http://www.trinity-electronics.com
> >> Custom Electronics Design and Manufacturing
> >>
> >> --
> >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >> View/change your membership options at
> >> mailman.mit.edu/mailman/listinfo/piclist
> >>
> >
> >
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

> Could you post a photo of the original problem so we could see if somehow
> you are interpreting it differently than we would?
>
> I just tried the physical circuit (I used a J310 because I don't have a
> 2N4860 and J310 seems very similar) and I can't get anything like the
> voltages they describe by making any one resistor open or shorted,
> regardless of whether I use a 10Mohm input impedance voltmeter or a 10G ohm
> impedance voltmeter. If I open the source resistor and measure Vs, I get
> about 3V with either the Rin=10Mohm meter or the Rin=10Gohm meter.
>
>
> On Mon, Sep 11, 2017 at 9:04 PM, James Burkart <TakeThisOuTjames.....TakeThisOuTburkartstudios.com>
> wrote:
>
> > Actually I meant Vgs closer to 0V, not Vg.
> >
> > --
> > Sincerely,
> >
> > James Burkart
> > *Filmmaker & Documentarian*
> >
> > *Burkart Studios*
> > 925.667.7175 | Personal
> > 415.738.2071 | Office
> >
> > *Web:* burkartstudios.com
> > *Facebook:* facebook.com/burkartstudios
> >
> > On Mon, Sep 11, 2017 at 7:02 PM, James Burkart <TakeThisOuTjamesKILLspamspamburkartstudios.com
> >
> > wrote:
> >
> > > Raising the value of Rs serves to increase negative biasing the gate,
> > > which raises the value of Vds. Lowering it brings Vg closer to 0V, but
> > > increases Id, and increases the voltage drop across Rd.
> > >
> > > Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this
> > case
> > > I do get 15V at Vd since there is virtually no current through the
> > > transistor (spice simulation shows 177pA) but then Vds becomes ~10V.
> > >
> > > --
> > > Sincerely,
> > >
> > > James Burkart
> > > *Filmmaker & Documentarian*
> > >
> > > *Burkart Studios*
> > > 925.667.7175 <(925)%20667-7175> | Personal
> > > 415.738.2071 <(415)%20738-2071> | Office
> > >
> > > *Web:* burkartstudios.com
> > > *Facebook:* facebook.com/burkartstudios
> > >
> > > On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <.....dwaynerRemoveMEplanet.eon.net>
> > > wrote:
> > >
> > >> Hi there, Sean.
> > >>
> > >> You are forgetting about current that flows through the gate resistor
> > >> to Ground.  This is a J-FET, so the gate diode junction is forward
> > >> biased if Rs is open.
> > >>
> > >> Another possibility that Rs is very high value.  I haven't bothered
> > >> to work out the math for the possible high value.
> > >>
> > >> dwayne
> > >>
> > >>
> > >> At 11:58 AM 9/11/2017, Sean Breheny wrote:
> > >> >I might be missing something but I don't think this problem is well
> > >> >designed. I think we can narrow it down to Rs being open but
> > technically
> > >> it
> > >> >isn't possible, as far as I can see, to get exactly the voltages
> > >> mentioned.
> > >> >Vd=15V implies that absolutely no current is flowing from the supply,
> > so
> > >> >there shouldn't be ANY voltage drop across the drain-source
> connection.
> > >> >
> > >> >Here's my train of thought:
> > >> >
> > >> >If Rd were open, Vd would be zero.
> > >> >If Rd were shorted, the current would be limited by the negative Vgs
> > >> which
> > >> >would develop (I am defining negative Vgs as Vs>Vg, which reverse
> > biases
> > >> >the gate junction for an N JFET), so there would be some Vds drop of
> > >> >several volts.
> > >> >
> > >> >If Rg were open, I think the FET behavior would tend toward the Vgs=0
> > >> >behavior where almost the maximum current flows, but then Vd would be
> > >> less
> > >> >than 15V.
> > >> >
> > >> >If Rg were shorted, the circuit would behave almost as if nothing
> were
> > >> >wrong, unless 15V was enough to cause reverse breakdown of the gate
> > >> >junction, but in that case Vd would be less than 15V since an
> excessive
> > >> >leakage current would flow.
> > >> >
> > >> >If Rs were shorted, Vs would be zero.
> > >> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the
> > closest
> > >> >to what we observe. In the real world, the 10Meg input impedance of a
> > >> >typical multimeter would probably produce something similar to what
> is
> > >> >claimed here (it would act as a very high value of Vs) but Vd would
> not
> > >> be
> > >> >identically 15V.
> > >> >
> > >> >
> > >> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <
> RemoveMEdwaynerspamBeGoneplanet.eon.net>
> > >> >wrote:
> > >> >
> > >> > > Hi there.
> > >> > >
> > >> > > Consider what happens if Rs goes open.  Also consider that the
> gate
> > >> > > junction becomes forward-biased when Vgs goes negative.
> > >> > >
> > >> > > dwayne
> > >> > >
> > >> > >
> > >> > > At 06:40 AM 9/11/2017, James Burkart wrote:
> > >> > > >Hello all!
> > >> > > >
> > >> > > >I am working on a lab for a class and we are given a simple
> > >> self-biased
> > >> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860,
> > >> Vdd =
> > >> > > >+15V.
> > >> > > >
> > >> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs =
> 14.9V.
> > >> > > >
> > >> > > >Assuming only one component can be bad, what is the likely
> problem?
> > >> > > >
> > >> > > >I built the circuit in MPLab and tried everything I could think
> of
> > to
> > >> > > >recreate the voltages, but everything I tried does not work.
> > >> Shorting Rd
> > >> > > >was my first thought, but that also results in Vds being 12.6V.
> > What
> > >> am I
> > >> > > >missing? Can anyone get me on the right track? I have shorted and
> > >> opened
> > >> > > >all resistors, the only thing I can't do (or don't know how to
> do)
> > is
> > >> > > >recreate a faulty FET.
> > >> > > >
> > >> > > >--
> > >> > > >Sincerely,
> > >> > > >
> > >> > > >James Burkart
> > >> > > >*Filmmaker & Documentarian*
> > >> > > >
> > >> > > >*Burkart Studios*
> > >> > > >925.667.7175 <(925)%20667-7175> | Personal
> > >> > > >415.738.2071 <(415)%20738-2071> | Office
> > >> > > >
> > >> > > >*Web:* burkartstudios.com
> > >> > > >*Facebook:* facebook.com/burkartstudios
> > >>
> > >>
> > >> --
> > >> Dwayne Reid   <spamBeGonedwayner@spam@spam_OUTplanet.eon.net>
> > >> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
> > >> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
> > >> http://www.trinity-electronics.com
> > >> Custom Electronics Design and Manufacturing
> > >>
> > >> --
> > >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > >> View/change your membership options at
> > >> mailman.mit.edu/mailman/listinfo/piclist
> > >>
> > >
> > >
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > mailman.mit.edu/mailman/listinfo/piclist
> >
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

> Sure thing!
>
> I saved the lab to a word doc and put it on my Google Drive.
> drive.google.com/file/d/0Bw1n2tiO8ikQVzlaekYyblVYaXM/
> view?usp=sharing
>
> --
> Sincerely,
>
> James Burkart
> *Filmmaker & Documentarian*
>
> *Burkart Studios*
> 925.667.7175 <(925)%20667-7175> | Personal
> 415.738.2071 <(415)%20738-2071> | Office
>
> *Web:* burkartstudios.com
> *Facebook:* facebook.com/burkartstudios
>
> On Mon, Sep 11, 2017 at 8:31 PM, Sean Breheny <shb7EraseMEcornell.edu> wrote:
>
>> Could you post a photo of the original problem so we could see if somehow
>> you are interpreting it differently than we would?
>>
>> I just tried the physical circuit (I used a J310 because I don't have a
>> 2N4860 and J310 seems very similar) and I can't get anything like the
>> voltages they describe by making any one resistor open or shorted,
>> regardless of whether I use a 10Mohm input impedance voltmeter or a 10G
>> ohm
>> impedance voltmeter. If I open the source resistor and measure Vs, I get
>> about 3V with either the Rin=10Mohm meter or the Rin=10Gohm meter.
>>
>>
>> On Mon, Sep 11, 2017 at 9:04 PM, James Burkart <RemoveMEjamesEraseMEspam_OUTburkartstudios.com>
>> wrote:
>>
>> > Actually I meant Vgs closer to 0V, not Vg.
>> >
>> > --
>> > Sincerely,
>> >
>> > James Burkart
>> > *Filmmaker & Documentarian*
>> >
>> > *Burkart Studios*
>> > 925.667.7175 | Personal
>> > 415.738.2071 | Office
>> >
>> > *Web:* burkartstudios.com
>> > *Facebook:* facebook.com/burkartstudios
>> >
>> > On Mon, Sep 11, 2017 at 7:02 PM, James Burkart <
>> @spam@jamesRemoveMEEraseMEburkartstudios.com>
>> > wrote:
>> >
>> > > Raising the value of Rs serves to increase negative biasing the gate,
>> > > which raises the value of Vds. Lowering it brings Vg closer to 0V, but
>> > > increases Id, and increases the voltage drop across Rd.
>> > >
>> > > Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this
>> > case
>> > > I do get 15V at Vd since there is virtually no current through the
>> > > transistor (spice simulation shows 177pA) but then Vds becomes ~10V.
>> > >
>> > > --
>> > > Sincerely,
>> > >
>> > > James Burkart
>> > > *Filmmaker & Documentarian*
>> > >
>> > > *Burkart Studios*
>> > > 925.667.7175 <(925)%20667-7175> | Personal
>> > > 415.738.2071 <(415)%20738-2071> | Office
>> > >
>> > > *Web:* burkartstudios.com
>> > > *Facebook:* facebook.com/burkartstudios
>> > >
>> > > On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <EraseMEdwayner@spam@planet.eon.net>
>> > > wrote:
>> > >
>> > >> Hi there, Sean.
>> > >>
>> > >> You are forgetting about current that flows through the gate resistor
>> > >> to Ground.  This is a J-FET, so the gate diode junction is forward
>> > >> biased if Rs is open.
>> > >>
>> > >> Another possibility that Rs is very high value.  I haven't bothered
>> > >> to work out the math for the possible high value.
>> > >>
>> > >> dwayne
>> > >>
>> > >>
>> > >> At 11:58 AM 9/11/2017, Sean Breheny wrote:
>> > >> >I might be missing something but I don't think this problem is well
>> > >> >designed. I think we can narrow it down to Rs being open but
>> > technically
>> > >> it
>> > >> >isn't possible, as far as I can see, to get exactly the voltages
>> > >> mentioned.
>> > >> >Vd=15V implies that absolutely no current is flowing from the
>> supply,
>> > so
>> > >> >there shouldn't be ANY voltage drop across the drain-source
>> connection.
>> > >> >
>> > >> >Here's my train of thought:
>> > >> >
>> > >> >If Rd were open, Vd would be zero.
>> > >> >If Rd were shorted, the current would be limited by the negative Vgs
>> > >> which
>> > >> >would develop (I am defining negative Vgs as Vs>Vg, which reverse
>> > biases
>> > >> >the gate junction for an N JFET), so there would be some Vds drop of
>> > >> >several volts.
>> > >> >
>> > >> >If Rg were open, I think the FET behavior would tend toward the
>> Vgs=0
>> > >> >behavior where almost the maximum current flows, but then Vd would
>> be
>> > >> less
>> > >> >than 15V.
>> > >> >
>> > >> >If Rg were shorted, the circuit would behave almost as if nothing
>> were
>> > >> >wrong, unless 15V was enough to cause reverse breakdown of the gate
>> > >> >junction, but in that case Vd would be less than 15V since an
>> excessive
>> > >> >leakage current would flow.
>> > >> >
>> > >> >If Rs were shorted, Vs would be zero.
>> > >> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the
>> > closest
>> > >> >to what we observe. In the real world, the 10Meg input impedance of
>> a
>> > >> >typical multimeter would probably produce something similar to what
>> is
>> > >> >claimed here (it would act as a very high value of Vs) but Vd would
>> not
>> > >> be
>> > >> >identically 15V.
>> > >> >
>> > >> >
>> > >> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <
>> @spam@dwaynerspam_OUT.....planet.eon.net>
>> > >> >wrote:
>> > >> >
>> > >> > > Hi there.
>> > >> > >
>> > >> > > Consider what happens if Rs goes open.  Also consider that the
>> gate
>> > >> > > junction becomes forward-biased when Vgs goes negative.
>> > >> > >
>> > >> > > dwayne
>> > >> > >
>> > >> > >
>> > >> > > At 06:40 AM 9/11/2017, James Burkart wrote:
>> > >> > > >Hello all!
>> > >> > > >
>> > >> > > >I am working on a lab for a class and we are given a simple
>> > >> self-biased
>> > >> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 =
>> 2N4860,
>> > >> Vdd =
>> > >> > > >+15V.
>> > >> > > >
>> > >> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs =
>> 14.9V.
>> > >> > > >
>> > >> > > >Assuming only one component can be bad, what is the likely
>> problem?
>> > >> > > >
>> > >> > > >I built the circuit in MPLab and tried everything I could think
>> of
>> > to
>> > >> > > >recreate the voltages, but everything I tried does not work.
>> > >> Shorting Rd
>> > >> > > >was my first thought, but that also results in Vds being 12.6V..
>> > What
>> > >> am I
>> > >> > > >missing? Can anyone get me on the right track? I have shorted
>> and
>> > >> opened
>> > >> > > >all resistors, the only thing I can't do (or don't know how to
>> do)
>> > is
>> > >> > > >recreate a faulty FET.
>> > >> > > >
>> > >> > > >--
>> > >> > > >Sincerely,
>> > >> > > >
>> > >> > > >James Burkart
>> > >> > > >*Filmmaker & Documentarian*
>> > >> > > >
>> > >> > > >*Burkart Studios*
>> > >> > > >925.667.7175 <(925)%20667-7175> | Personal
>> > >> > > >415.738.2071 <(415)%20738-2071> | Office
>> > >> > > >
>> > >> > > >*Web:* burkartstudios.com
>> > >> > > >*Facebook:* facebook.com/burkartstudios
>> > >>
>> > >>
>> > >> --
>> > >> Dwayne Reid   <spamBeGonedwaynerEraseMEplanet.eon.net>
>> > >> Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
>> > >> 780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
>> > >> http://www.trinity-electronics.com
>> > >> Custom Electronics Design and Manufacturing
>> > >>
>> > >> --
>> > >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> > >> View/change your membership options at
>> > >> mailman.mit.edu/mailman/listinfo/piclist
>> > >>
>> > >
>> > >
>> > --
>> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> > View/change your membership options at
>> > mailman.mit.edu/mailman/listinfo/piclist
>> >
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> mailman.mit.edu/mailman/listinfo/piclist
>>
>
>

> Sure thing!
>
> I saved the lab to a word doc and put it on my Google Drive.
> drive.google.com/file/d/0Bw1n2tiO8ikQVzlaekYyblVYaXM/
> view?usp=sharing
>
> --
> Sincerely,
>
> James Burkart
> *Filmmaker & Documentarian*
>
> *Burkart Studios*
> 925.667.7175 | Personal
> 415.738.2071 | Office
>
> *Web:* burkartstudios.com
> *Facebook:* facebook.com/burkartstudios
>
>
>

> Hmmm - it is as I had envisioned it so there is no major revelation.
>
> For cases 1 and 3, did you get that R3 (Rs) is shorted for #1 and for #3
> that the JFET is bad (D-S open)?
>
> On Mon, Sep 11, 2017 at 10:37 PM, James Burkart <.....james@spam@EraseMEburkartstudios.com>
> wrote:
>
> > Sure thing!
> >
> > I saved the lab to a word doc and put it on my Google Drive.
> > drive.google.com/file/d/0Bw1n2tiO8ikQVzlaekYyblVYaXM/
> > view?usp=sharing
> >
> > --
> > Sincerely,
> >
> > James Burkart
> > *Filmmaker & Documentarian*
> >
> > *Burkart Studios*
> > 925.667.7175 | Personal
> > 415.738.2071 | Office
> >
> > *Web:* burkartstudios.com
> > *Facebook:* facebook.com/burkartstudios
> >
> >
> >
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

>Dwane - no, for an n jfet the gate would only be forward biased if it were
>higher than the source in voltage (gate more positive than source). Jfets
>are always depletion mode devices so they are on with no gate bias and turn
>off when reverse bias is applied to the gate-channel junction
>
>
>On Sep 11, 2017 3:10 PM, "Dwayne Reid" <.....dwaynerRemoveMEplanet.eon.net> wrote:
>
>Hi there, Sean.
>
>You are forgetting about current that flows through the gate resistor
>to Ground.  This is a J-FET, so the gate diode junction is forward
>biased if Rs is open.
>
>Another possibility that Rs is very high value.  I haven't bothered
>to work out the math for the possible high value.
>
>dwayne
>
>
>At 11:58 AM 9/11/2017, Sean Breheny wrote:
> >I might be missing something but I don't think this problem is well
> >designed. I think we can narrow it down to Rs being open but technically it
> >isn't possible, as far as I can see, to get exactly the voltages mentioned.
> >Vd=15V implies that absolutely no current is flowing from the supply, so
> >there shouldn't be ANY voltage drop across the drain-source connection.
> >
> >Here's my train of thought:
> >
> >If Rd were open, Vd would be zero.
> >If Rd were shorted, the current would be limited by the negative Vgs which
> >would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
> >the gate junction for an N JFET), so there would be some Vds drop of
> >several volts.
> >
> >If Rg were open, I think the FET behavior would tend toward the Vgs=0
> >behavior where almost the maximum current flows, but then Vd would be less
> >than 15V.
> >
> >If Rg were shorted, the circuit would behave almost as if nothing were
> >wrong, unless 15V was enough to cause reverse breakdown of the gate
> >junction, but in that case Vd would be less than 15V since an excessive
> >leakage current would flow.
> >
> >If Rs were shorted, Vs would be zero.
> >If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
> >to what we observe. In the real world, the 10Meg input impedance of a
> >typical multimeter would probably produce something similar to what is
> >claimed here (it would act as a very high value of Vs) but Vd would not be
> >identically 15V.
> >
> >
> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <.....dwaynerSTOPspam@spam@planet.eon.net>
> >wrote:
> >
> > > Hi there.
> > >
> > > Consider what happens if Rs goes open.  Also consider that the gate
> > > junction becomes forward-biased when Vgs goes negative.
> > >
> > > dwayne
> > >
> > >
> > > At 06:40 AM 9/11/2017, James Burkart wrote:
> > > >Hello all!
> > > >
> > > >I am working on a lab for a class and we are given a simple self-biased
> > > >N-channel JFET circuit: Rd = 4.7k, Rs = 1k, Rg = 2M, Q1 = 2N4860, Vdd =
> > > >+15V.
> > > >
> > > >Then we are given the scenario: Vds = 66.5mV, Vd = 15V, Vs = 14.9V.
> > > >
> > > >Assuming only one component can be bad, what is the likely problem?
> > > >
> > > >I built the circuit in MPLab and tried everything I could think of to
> > > >recreate the voltages, but everything I tried does not work. Shorting
>Rd
> > > >was my first thought, but that also results in Vds being 12.6V. What
>am I
> > > >missing? Can anyone get me on the right track? I have shorted and
>opened
> > > >all resistors, the only thing I can't do (or don't know how to do) is
> > > >recreate a faulty FET.
> > > >
> > > >--
> > > >Sincerely,
> > > >
> > > >James Burkart
> > > >*Filmmaker & Documentarian*
> > > >
> > > >*Burkart Studios*
> > > >925.667.7175 | Personal
> > > >415.738.2071 | Office
> > > >
> > > >*Web:* burkartstudios.com
> > > >*Facebook:* facebook.com/burkartstudios
>
>
>--
>Dwayne Reid   <dwaynerEraseME@spam@planet.eon.net>
>Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
>780-489-3199 voice   780-487-6397 fax   888-489-3199 Toll Free
>http://www.trinity-electronics.com
>Custom Electronics Design and Manufacturing
>
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