Searching \ for '[EE]: Fw: [AR] SOT: 60Gips at 500mW for ~$1k' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/index.htm?key=sot+60gips+500mw
Search entire site for: 'Fw: [AR] SOT: 60Gips at 500mW for ~$1k'.

Exact match. Not showing close matches.
PICList Thread
'[EE]: Fw: [AR] SOT: 60Gips at 500mW for ~$1k'
2002\07\19@095432 by Russell McMahon

face
flavicon
face
From another list (a rocketry one ! :-)  ).
Thought people may be intertested where things MAY be going.

       RM

__________________________________________


I don't know if anyone has looked at Chuck Moore's controller chip design
but its pretty wild.  He claims he can get you the part in lots of 25 for
$14k (and that was around a year ago).  The integrated system weight and
power consumption are very low even at 60 Gips (of course a lot of that
could go to waste without some difficult programming).  Forth is a drawback
(unless you like Forth and I admit to having a Forth problem) or you are
doing assembly programming anyway.

http://www.colorforth.com/25x.html

25x Microcomputer
An array of 25 microcomputers on a 7 sq mm die.

Features

.2 sq mm asynchronous microcomputer core
5 x 5 array of cores: 60,000 Mips
5 horizontal, 5 vertical parallel interconnect buses: 180 Ghz bandwidth
Specialized computers to interface off-chip.
Max power 500 mW @ 1.8 V, with 25 computers running
100mAh battery life is 1 year, with 1 computer running throttled
64-pin SOIC: mirrored pin-out to 4ns cache SRAM
Array chips on 2-sided PCB

Description

Availability of the tiny (.2 sq mm), asynchronous X18 microcomputer core
naturally suggested arraying it on a chip. Its extremely low power (20 mW)
made that feasible. A 5x5 array was chosen to fit on a 7 sq mm die, the
smallest available prototype, though larger arrays are possible. 25
computers running at 2400 Mips is a total of 60,000 Mips. An unlimited
supply.
Communication among the computers is provided by a network with 5 horizontal
and 5 vertical buses. Each computer has 2 bus registers to access a
horizontal and a vertical bus. Each bus is 18-bits wide and can run at 1
GHz. All 10 buses can be active at once connecting a 20-computer subset. So
total bandwidth is 180 GHz.
Each computer can customized. Registers are added to the 16 processors at
the edge of the array and connected to package pins. Each computer is
responsible for a particular interface. Protocols are implemented with
software.

SRAM controller
Flash controller
4 serial controllers
USB controller
D/A controller
A/D controller

After booting from ROM, the computers await code downloaded from one of
these interfaces.

Pinout

Chosen to be the mirror image of an 18-bit cache memory chip. This is the
fastest memory available, with 4 ns access. Its package is a 100-pin SOIC.
The 18-bit Multicomputer thus has 256K words of external memory in 1 chip.

Putting the Multicomputer chip on the top of a 2-sided PCB and the SRAM chip
on the bottom gives a very small footprint. A decoupling capacitor is the
only other component needed. An array of such pairs is a multicomputer
board. Connecting Multicomputer to SRAM is trivial, with mm traces. Routing
for power and a serial network is also easy. Computers load code from the
network.

A parallel computer with 60Gips nodes! Power is determined by the SRAM.

Cost/Availability

The chip is awaiting funding. If interested, contact
spam_OUTchipchuckTakeThisOuTspammindspring.com
A 7 sq mm die, packaged, will cost about $1 in quantity 1,000,000. Cost per
Mip is 0.
25 prototypes can be obtained from MOSIS for $14,000 with 16 week
turn-around. The TSMC .18um process has monthly submissions.

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email .....listservKILLspamspam@spam@mitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@104017 by Alan B. Pearce

face picon face
> A decoupling capacitor is the
>only other component needed.

I suspec tthat given the number of capacitors that get mounted around a
Pentium processor that requiring only one capacitor is likely to lead to
problems :))

And the way I read the piece, this capacitor is shared between the CPU and
the high speed ram. Somehow I suspect this is looking for trouble.

Wish I had $14K and the time to play with it, my assemble/test turnround
times might shorten :) Least there would be no problems with simulator speed
:)

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email listservspamKILLspammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@134347 by Brendan Moran

flavicon
face
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Wow.  Uh.... Wow.  Now, that sounds like the basis for one heck of a
Linux box.  So, is there a C compiler in progress for this thing?

If the cost per weren't prohibitively expensive (assuming $14k for
25, that's $560, which is too much for me to pay for a chip for
myself.  And prices likely are higher for unit quantities) for me,
personally, I'd say I'd get one just to experiment with :)

- --Brendan

{Quote hidden}

-----BEGIN PGP SIGNATURE-----
Version: PGPfreeware 6.5.8 for non-commercial use <http://www.pgp.com>

iQA/AwUBPThP3wVk8xtQuK+BEQKnnwCghZZNSIXnCd/nTqrkZJb3hG6emyoAoMce
iWsWUdvB1vRpZzHaon+ucgXW
=BpKO
-----END PGP SIGNATURE-----

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email .....listservKILLspamspam.....mitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@140526 by D. Jay Newman

flavicon
face
The heck with Linux: put a Java VM on the sucker and base the OS directly
on that.

With memory to match the speed, I bet I could do some real-time vision
processing that would blow anything I've seen out of the water.

Maybe next year.  :)

{Quote hidden}

--
D. Jay Newman                      !  Live fast,
jayspamspam_OUTsprucegrove.com                !    Die young,
http://www.sprucegrove.com/~jay/   !      And leave a flesh eating corpse!

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email @spam@listservKILLspamspammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@142416 by lexandre_Guimar=E3es?=

flavicon
face
Hi,

   I personally saw the F21 running inside a mouse case in 1994 and it was
faster than a 486 by much !! The idea of small and fast stack computers is
so nice that I do not understand how it never caught up. And the guy that is
making the project understands stacks better than anyone else, he invented
Forth.

   I would love to put my hands on that thing and make it rock !

Best regards,
Alexandre Guimaraes

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email KILLspamlistservKILLspamspammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@142559 by Brendan Moran

flavicon
face
> The heck with Linux: put a Java VM on the sucker and base the OS directly
> on that.

Sorry, didn't think of that.  I'm a solder/C++/assembly programmer (In that
order).

> With memory to match the speed, I bet I could do some real-time vision
> processing that would blow anything I've seen out of the water.

If anyone does something sensible with it (in terms of OS), it should blow
the *PC* out of the water.

I can see one of us geeks now... "Lets see... 2.2GHz (should be about
8.8GIPS) with Linux, or 60GIPS with Junix... Hmmmm...." (Junix = java linux,
if there is such a thing)

--Brendan

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email RemoveMElistservTakeThisOuTspammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@150940 by Peter L. Peres

picon face
On Fri, 19 Jul 2002, Brendan Moran wrote:

>> The heck with Linux: put a Java VM on the sucker and base the OS directly
>> on that.
>
>Sorry, didn't think of that.  I'm a solder/C++/assembly programmer (In that
>order).
>
>> With memory to match the speed, I bet I could do some real-time vision
>> processing that would blow anything I've seen out of the water.
>
>If anyone does something sensible with it (in terms of OS), it should blow
>the *PC* out of the water.

Anything with a relatively flat memory model and no need for six tons of
legacy junk to run peripherals no-one even remembers anymore will outclass
a PC in the same price class.

Peter

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email spamBeGonelistservspamBeGonespammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@151951 by Brendan Moran

flavicon
face
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

> Anything with a relatively flat memory model and no need for six
> tons of legacy junk to run peripherals no-one even remembers
> anymore will outclass a PC in the same price class.

When was the last time you used a serial or parallel port?  Or anyone
else here, for that matter?  I think that really, the only legacy
stuff that can be dropped sensibly is the ISA port.  Or, what were
you thinking of?

- --Brendan

-----BEGIN PGP SIGNATURE-----
Version: PGPfreeware 6.5.8 for non-commercial use <http://www.pgp.com>

iQA/AwUBPThmCAVk8xtQuK+BEQJiagCeP4KgY6WGCPXdoC3IxqB8VtjH9sYAnRfq
VNnq/DXfwh/JdHUN4J6Tl6a/
=brtG
-----END PGP SIGNATURE-----

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email TakeThisOuTlistservEraseMEspamspam_OUTmitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@153902 by R. Michael O'Bannon, Ph.D.

picon face
>When was the last time you used a serial or parallel port?  Or anyone
else here, for that matter?  I think that really, the only legacy
stuff that can be dropped sensibly is the ISA port.  Or, what were
you thinking of?

I use them everyday for several different applications and plan to for the forseeable future.  Perhaps you need to rejoin the real world of users.

Michael

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email RemoveMElistservspamTakeThisOuTmitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@155347 by Peter L. Peres

picon face
On Fri, 19 Jul 2002, Brendan Moran wrote:

>-----BEGIN PGP SIGNED MESSAGE-----
>Hash: SHA1
>
>> Anything with a relatively flat memory model and no need for six
>> tons of legacy junk to run peripherals no-one even remembers
>> anymore will outclass a PC in the same price class.
>
>When was the last time you used a serial or parallel port?  Or anyone
>else here, for that matter?  I think that really, the only legacy
>stuff that can be dropped sensibly is the ISA port.  Or, what were
>you thinking of?

Of course you know what the PIC was originally designed for (the General
Instrument design, not the current PROM based thing). Hehe. <duck>

As to what should be dropped, I'd start with x86 compatible code, which is
horrible at the machine level, the CPU, the three big modes (protected,
unprotected and one emulating the other in some hermaphrodite
arrangement). I'd lose all non-open source code on the way, but I could
run it in emulation, maybe faster than originally intended. A RISC
coprocessor on a PCI card could supply up to 16 512kbps serial links.
Another could supply several parallel port equivalents. Same for
firewaire, whatever you need. I'd get an embeddable board with standard
connections, with no idiosynchratic 'on board' things, with peripheral
cards, cpu sets and main boards manufactured by several makers. Kind of
like a PC without the mess that's inside them nowadays.

Peter

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email listservEraseMEspam.....mitvma.mit.edu with SET PICList DIGEST in the body


2002\07\19@215058 by Michael Rigby-Jones

flavicon
face
> -----Original Message-----
> From: Alan B. Pearce [SMTP:EraseMEA.B.PearcespamRL.AC.UK]
> Sent: Friday, July 19, 2002 3:39 PM
> To:   RemoveMEPICLISTEraseMEspamEraseMEMITVMA.MIT.EDU
> Subject:      Re: [EE]: Fw: [AR] SOT: 60Gips at 500mW for ~$1k
>
> > A decoupling capacitor is the
> >only other component needed.
>
> I suspec tthat given the number of capacitors that get mounted around a
> Pentium processor that requiring only one capacitor is likely to lead to
> problems :))
>
Did you notice the power consumption?  A typical P4 is probably consuming
somewhere in the region of 50-70Watts which necesitates the heavy supply
decoupling. This thing is allegedly only drawing 500mW maximum.

Regards

Mike

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email RemoveMElistservspam_OUTspamKILLspammitvma.mit.edu with SET PICList DIGEST in the body


2002\07\20@062739 by Michael Rigby-Jones

flavicon
face
> -----Original Message-----
> From: Alan B. Pearce [SMTP:RemoveMEA.B.PearceTakeThisOuTspamspamRL.AC.UK]
> Sent: Friday, July 19, 2002 3:39 PM
> To:   EraseMEPICLISTspamspamspamBeGoneMITVMA.MIT.EDU
> Subject:      Re: [EE]: Fw: [AR] SOT: 60Gips at 500mW for ~$1k
>
> > A decoupling capacitor is the
> >only other component needed.
>
> I suspec tthat given the number of capacitors that get mounted around a
> Pentium processor that requiring only one capacitor is likely to lead to
> problems :))
>
Did you notice the power consumption?  A typical P4 is probably consuming
somewhere in the region of 50-70Watts which necesitates the heavy supply
decoupling. This thing is allegedly only drawing 500mW maximum.

Regards

Mike

--
http://www.piclist.com hint: To leave the PICList
RemoveMEpiclist-unsubscribe-requestKILLspamspammitvma.mit.edu


2002\07\20@234315 by Dale Botkin

flavicon
face
On Fri, 19 Jul 2002, D. Jay Newman wrote:

> The heck with Linux: put a Java VM on the sucker and base the OS directly
> on that.

Hmm, yeah, you'd get at least the performance of...  say...  a 486/66 out
of it then...  8-P

Dale
(anybody remember UCSD P-System?  Anyone?  Buehler?)

--
http://www.piclist.com hint: To leave the PICList
piclist-unsubscribe-requestSTOPspamspamspam_OUTmitvma.mit.edu


2002\07\21@064503 by Bob Ammerman

picon face
> Dale
> (anybody remember UCSD P-System?  Anyone?  Buehler?)

Yes, and believe it or not, rather fondly.

Bob Ammerman
RAm Systems

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@100812 by lexandre_Guimar=E3es?=

flavicon
face
Hi,


> (anybody remember UCSD P-System?  Anyone?  Buehler?)


   I should never forget my first computer language ! It worked so nicely
and you could get from Unix to CPM using the same intermediate code !

   Java is basically the same thing and Chuck's chip is basically a
processor that can execute tha basic Forth words in hardware. It should be
as fast as it gets. You could do a nice multitask kernel over it in a few
kbytes.

   I wish I had some good money to spare. His way of doing processors
really has the potential to revolutionize many markets. The problem is that
he does not have the money and has some ideas that are really not
mainstream. Someone would have to guide his genius to make marketable parts
before he goes to the top of speed things. I still have hope he will suceed
and get us some very nice toys to play with.

Best regards,
Alexandre Guimaraes

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@104851 by Roman Black

flavicon
face
Alexandre Guimarães wrote:

>     I wish I had some good money to spare. His way of doing processors
> really has the potential to revolutionize many markets. The problem is that
> he does not have the money and has some ideas that are really not
> mainstream. Someone would have to guide his genius to make marketable parts
> before he goes to the top of speed things. I still have hope he will suceed
> and get us some very nice toys to play with.


This thread has been interesting, i'm wondering if
a number of us (piclisters) got together and put
say $500 USD in each, could we get a "super-pic"
made at one of the custom chip plants?? A chip that
will be able to run our existing legacy PIC RISC
code, but at super-high speeds??

Strikes me that the PIC processor itself is a simple
enough device, why can't we get them made to do
1GHz etc?? They are much simpler than something like
a Pentium, shorter distances from processor to ram
etc, surely we can get them made with similar
speeds? I'm sincerely curious as to how much
that would cost total, and per unit, and the lead
time before the group actually get the chips.
-Roman

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@110837 by Alexandre Souza

flavicon
face
>
>
>Strikes me that the PIC processor itself is a simple
>enough device, why can't we get them made to do
>1GHz etc?? They are much simpler than something like
>a Pentium, shorter distances from processor to ram
>etc, surely we can get them made with similar
>speeds? I'm sincerely curious as to how much
>that would cost total, and per unit, and the lead
>time before the group actually get the chips.
>-Roman
>
>
   Although you have an interesting idea, Roman, I think that is easier
(and a L O T cheaper) to use newer/faster parts, or a choice of another
processors. Scenix and ATMEL comes to mind. Of course, it won't do 60
GIPS, but does we need this kind of speed?

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@132949 by Peter L. Peres

picon face
On Mon, 22 Jul 2002, Roman Black wrote:

{Quote hidden}

I want a PIC with a real stack and accessible stack pointer and NO PAGES
OR BANKS. Make the word as wide as you wish, make gotos and calls whatever
you wish, NO MORE PAGING AND BANKING. The PIC has grown too big for this
ancient kludge imho.

Peter

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@164853 by Dale Botkin

flavicon
face
On Sun, 21 Jul 2002, Bob Ammerman wrote:

> > Dale
> > (anybody remember UCSD P-System?  Anyone?  Buehler?)
>
> Yes, and believe it or not, rather fondly.

Yeah...  but it died off at least in part because it could turn your nice
fast 2MHz or whatever system into a crawler.  Kind of like - no, I don't
want to start a new holy war on Sunday.  Cool idea, but extremely
inefficient use of CPU resources.

Dale

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@172723 by Matt Pobursky

flavicon
face
On Sun, 21 Jul 2002 20:27:53 +0300, Peter L. Peres wrote:
>I want a PIC with a real stack and accessible stack pointer and NO
>PAGES OR BANKS. Make the word as wide as you wish, make gotos and
>calls whatever you wish, NO MORE PAGING AND BANKING. The PIC has grown
>too big for this ancient kludge imho.

It's called an AVR... ;-)

Matt Pobursky
Maximum Performance Systems

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@173546 by Alexandre Souza

flavicon
face
>
>
>>I want a PIC with a real stack and accessible stack pointer and NO
>>PAGES OR BANKS. Make the word as wide as you wish, make gotos and
>>calls whatever you wish, NO MORE PAGING AND BANKING. The PIC has grown
>>too big for this ancient kludge imho.
>>
>>
>It's called an AVR... ;-)
>
>
   HAUHAUHAUHUAHUAHUHAUHUAHUAUHAUHAUUHAUHA, Boa papito! :oD

   (Sorry, I'm rolling on the floor, I cannot stop laughting) ;oD

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\21@174251 by lexandre_Guimar=E3es?=

flavicon
face
Hi, Dale


> On Sun, 21 Jul 2002, Bob Ammerman wrote:
>
> > > Dale
> > > (anybody remember UCSD P-System?  Anyone?  Buehler?)
> >
> > Yes, and believe it or not, rather fondly.
>
> Yeah...  but it died off at least in part because it could turn your nice
> fast 2MHz or whatever system into a crawler.  Kind of like - no, I don't
> want to start a new holy war on Sunday.  Cool idea, but extremely
> inefficient use of CPU resources.

   That is exactly the beauty of Chuck's design !! It runs "high level"
stack machine words in hardware. You can see it almost as P-code running
really fast.

   Roman's idea of making a high speed PIC clone does not sound too good to
me :-) For that we can buy Scenix cpu's. Putting flash or eeprom to run at
1ghz is undoable nowadays. Besides that Chuck's design is much more
efficient in silicon that a PIC ! It is really very different from what has
been done before. We could think about funding it :-) Not PIC compatible but
we can make a translator and that thing would still run hundreds of times
faster than our little Pic's ;-)

   Submitting a prototype in a multi chip wafer runs for about Us$ 10000 to
Us$ 15000 depending on the process you chose. Expensive but doable for many
projects. Some design tools are available for free !!! We could make a PIC
clone but it would be hardly worthwhile IMHO. Making a chip like Chuck's
beasties appeal to me. We could use any high level language and still atain
very high speeds. I would like to see a small matchbox doing image
recognition :-)

Best regards,
Alexandre Guimaraes

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


2002\07\22@044825 by Alan B. Pearce
face picon face
> > > Dale
> > > (anybody remember UCSD P-System?  Anyone?  Buehler?)
> >
> > Yes, and believe it or not, rather fondly.
>
> Yeah...  but it died off at least in part because it could turn your nice
> fast 2MHz or whatever system into a crawler.  Kind of like - no, I don't
> want to start a new holy war on Sunday.  Cool idea, but extremely
> inefficient use of CPU resources.

I believe the major cause of its death was commercial greed. The story I
heard was that when the 8086 version came out, people who had been using the
8080 version wished to buy just the p-code engine for the 8086 version, but
found that they had to purchase full development systems, effectively
duplicating the 8080 development system they already had, and IIRC at a
somewhat higher cost.

Response was "stuff you mate, we'll do it another way".

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics


2002\07\22@125353 by Peter L. Peres

picon face
On Sun, 21 Jul 2002, Matt Pobursky wrote:

>On Sun, 21 Jul 2002 20:27:53 +0300, Peter L. Peres wrote:
>>I want a PIC with a real stack and accessible stack pointer and NO
>>PAGES OR BANKS. Make the word as wide as you wish, make gotos and
>>calls whatever you wish, NO MORE PAGING AND BANKING. The PIC has grown
>>too big for this ancient kludge imho.
>
>It's called an AVR... ;-)

I can't buy them in small qty. here ... I can buy 12C and 16F pics.

Peter

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics


2002\07\22@190130 by Brendan Moran

flavicon
face
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

> This thread has been interesting, i'm wondering if
> a number of us (piclisters) got together and put
> say $500 USD in each, could we get a "super-pic"
> made at one of the custom chip plants?? A chip that
> will be able to run our existing legacy PIC RISC
> code, but at super-high speeds??
>
> Strikes me that the PIC processor itself is a simple
> enough device, why can't we get them made to do
> 1GHz etc?? They are much simpler than something like
> a Pentium, shorter distances from processor to ram
> etc, surely we can get them made with similar
> speeds? I'm sincerely curious as to how much
> that would cost total, and per unit, and the lead
> time before the group actually get the chips.
> -Roman

With any luck, I'd go for that next summer.  Maybe all those of us
who like the idea could have something hashed out by then, or perhaps
a year later.

I think there are some Xilinx people (and maybe others with
Verilog/VHDL experience) on this list, maybe they could help us out
with the design, though I guess designing for silicon would be a
little different from designing for FPGA's.

Here's my list of desired capabilities:
*16-bit core
*built in mult and div
*completely stack oriented
*built-in context saving on interrupts
*context switching capability and multiple stacks for multitasking
*each stack being 256 bytes+
*swi (software interrupt) ability for ease of multitasking
*Von Neuman architecture
*8/16-bit instruction word with optional data words to follow
*IO mapped to memory space
*4 FPGA IO blocks to allow programmable IO capability
*1k+ RAM outside of stack
*32k+ Flash without LVP (to save on space and make the durn thing
cheaper)
*768 bytes+ EEPROM
*UART, I2C, SPI capability outside of FPGA
*Miscellaneous other things that I've forgotten

Likes?  Dislikes?  Ideas?  Helpful skills?
- --Brendan

-----BEGIN PGP SIGNATURE-----
Version: PGPfreeware 6.5.8 for non-commercial use <http://www.pgp.com>

iQA/AwUBPTyOwgVk8xtQuK+BEQLcnACdGSpiE8IrDVIi00ND+tFjvCknekgAn09h
zv7tdrfVNkbCHkCE65Xh2ZM8
=kWHC
-----END PGP SIGNATURE-----

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics


More... (looser matching)
- Last day of these posts
- In 2002 , 2003 only
- Today
- New search...