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'[EE]: EAGLE'
2002\11\02@083142 by 9-2?Q?samo_benedi=E8i=E8?=

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Hi!

When I start autorouter in EAGLE, I keep getting this warning: "Unreachable
SMD-pad at (x, y)", even if this  32 pin QFP package part is alone on the
board. What can I do about it? Thanks, Samo

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2002\11\02@084220 by Olin Lathrop

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> When I start autorouter in EAGLE, I keep getting this warning:
"Unreachable
> SMD-pad at (x, y)", even if this  32 pin QFP package part is alone on
the
> board. What can I do about it?

Most likely the autorouter grid setting is too coarse.  Try making it half
the pin pitch of the SMD device, although this may make is significantly
slower.  I've had some jobs that took a few hours to autoroute due to fine
pitch SMD, but it did a nice job in the end.

By the way, I always use more optimization passes than the default setup
does.  With the right parameters in 8 optimization passes you can get a
significant reduction in vias and traces that aren't restricted to
horizontal or vertical.


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2002\11\02@160414 by William Chops Westfield

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   By the way, I always use more optimization passes than the default setup
   does.  With the right parameters in 8 optimization passes you can get a
   significant reduction in vias and traces that aren't restricted to
   horizontal or vertical.

I hadn't thought of that.  Are you using one of the cadsoft-provided ctl
files, or are you willing to post what you are using?

Thanks
Bill W

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2002\11\02@171511 by Olin Lathrop

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part 1 668 bytes content-type:text/plain; (decoded 7bit)

> I hadn't thought of that.  Are you using one of the cadsoft-provided ctl
> files, or are you willing to post what you are using?

I didn't know the CTL files were plain text until you asked me to post
one.  OK, see attached.  This is one I used recently on a two sided board.
I wanted the top to be as much a ground plane as possible, so set a high
cost for it.  Note how some of the routing pass is adjusted for finding a
solution - any solution.  The remaining optimization passes then try to
improve on the answer by successively reducing the penalty for following
the preferred direction and making vias more expensive.


part 2 2873 bytes content-type:application/octet-stream; (decode)

part 3 279 bytes

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2002\11\03@063149 by Roman Black

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Olin Lathrop wrote:
>
> > When I start autorouter in EAGLE, I keep getting this warning:

> Most likely the autorouter grid setting is too coarse.  Try making it half
> the pin pitch of the SMD device, although this may make is significantly
> slower.  I've had some jobs that took a few hours to autoroute due to fine
> pitch SMD, but it did a nice job in the end.


Olin, you sound skilled with Eagle, any idea
how to get covered (masked) vias? :o)
-Roman

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2002\11\03@081548 by Olin Lathrop

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> Olin, you sound skilled with Eagle, any idea
> how to get covered (masked) vias? :o)

I don't have it in front of me right now, but in the DRC options (I think)
there is an option that sets what size vias get covered with solder mask.


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2002\11\03@092236 by Roman Black

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Olin Lathrop wrote:
>
> > Olin, you sound skilled with Eagle, any idea
> > how to get covered (masked) vias? :o)
>
> I don't have it in front of me right now, but in the DRC options (I think)
> there is an option that sets what size vias get covered with solder mask.


Thanks Olin, I checked options>set>DRC but
still couldn't find it. Maybe my version of
Eagle is too old??
-Roman

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2002\11\03@113016 by David Harris

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Hi-
I just tried it: DRC -> Masks -> limit -- set it just bigger than your via
size.  I am using 4.09r2.
David

Roman Black wrote:

{Quote hidden}

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2002\11\03@181821 by Olin Lathrop

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> Thanks Olin, I checked options>set>DRC but
> still couldn't find it. Maybe my version of
> Eagle is too old??

I am using the current version of Eagle (version 4).

I just fired up Eagle and checked.  Go to a board layout and run TOOLS >
DRC.  This brings up an applet window with 9 tabs.  The second tab from the
right is labeled MASKS.  In it is a parameter called LIMIT.  This can be
used to adjust the maximum size of vias that will be covered by solder mask.


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2002\11\04@094237 by Roman Black

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Olin Lathrop wrote:
>
> > Thanks Olin, I checked options>set>DRC but
> > still couldn't find it. Maybe my version of
> > Eagle is too old??
>
> I am using the current version of Eagle (version 4).
>
> I just fired up Eagle and checked.  Go to a board layout and run TOOLS >
> DRC.  This brings up an applet window with 9 tabs.  The second tab from the
> right is labeled MASKS.  In it is a parameter called LIMIT.  This can be
> used to adjust the maximum size of vias that will be covered by solder mask.


Thanks, will try that. :o)
-Roman

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2002\11\05@074559 by Roman Black

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Olin Lathrop wrote:
>
> > Thanks Olin, I checked options>set>DRC but
> > still couldn't find it. Maybe my version of
> > Eagle is too old??
>
> I am using the current version of Eagle (version 4).
>
> I just fired up Eagle and checked.  Go to a board layout and run TOOLS >
> DRC.  This brings up an applet window with 9 tabs.  The second tab from the
> right is labeled MASKS.  In it is a parameter called LIMIT.  This can be
> used to adjust the maximum size of vias that will be covered by solder mask.


Thank you Olin and David, I checked in Eagle
3.55 and it took a while to find, it's under
options->set->mask->set_stop_limit
which is not intuitive at all, my major gripe
with Eagle. It's a PITA to use unless I suppose
you've been using it since the text command days
and know what all the obscure commands mean.

Vias are covered now, thank you everyone. :o)
-Roman

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2002\11\05@113936 by William Chops Westfield

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   Thank you Olin and David, I checked in Eagle 3.55 and it took a
   while to find ... which is not intuitive at all, my major gripe
   with Eagle. It's a PITA to use unless I suppose you've been using
   it since the text command days and know what all the obscure
   commands mean.

Roman: you should try Eagle 4.x; I had similar complaints against
3.55 when I briefly tried it, but 4.x was MUCH better - many of
the things that used to be obscure commands now have GUI menus and
the default setup makes libary searching much easier, for instance.

BillW

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2002\11\05@115424 by Robert E. Griffith

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What's the issue with covering/not covering vias?  Is it just whether you
want to use the via as a test point or not?  Why would Eagle make it so that
there is a fixed size to transition from covered to not covered?

--BobG

{Original Message removed}


'[EE]: Eagle'
2002\12\19@203033 by Justin Grimm
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Is there any way to get a negative image of a pcb in Eagle? What I mean is
if the bottom layer tracks are blue, can I negative the image so that
everything else would be blue and the tracks transparent?

And then be able to print this negative.

Thanks
Justin

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2002\12\19@210208 by Pang

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Sorry for not including the tag in previous mail



> Hi Justin,
>
> AFAIK, you cannot do it in Eagle, but you can do it through the Printer
> settings. Goto Printer->Properties->Graphics and select 'Print as negative
> image.'
>
> I am not sure if there are other way, perhaps you should send a mail to
the
> Eagle user chat  or Eagle support newsgroup.
>
> The bad thing about doing the settings through the Printers properties, (
> which I think you already know of ) is that if your circuit size is less
> than a size of the paper defined, then the remaining part will also be
> printed with black. To reduce the wastage, you can actually, define a
custom
> size paper. But they will still have a minimum range.
>
> Good Luck.
>
>
> {Original Message removed}

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