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'[EE]: Divide by 3 - yet another cheapo design chal'
2002\05\27@014842 by Russell McMahon

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> >I love these "cheap" challenges!

OK here's another then ...
This is for another application (and another customer) from the last one.

As noted in the last challenge thread, standard flip flops and counters
without Schmitt trigger inputs have limits on maximum rise and fall times.
Real world signals can challenge these severely.

I have been asked to divide a digital signal by 3.
The input is a 3 volt signal produced by either a hall sensor or a reed
switch.
The signal idles at 3 volts and drops to ground for a brief period as the
sensor is triggered.
Input speed is from about 3 to 70 cycles per second (on a motor pulley).

Finished cost is paramount.

Using HC CMOS ICs I tried using a standard dual JK divide by 3 (2 gates in a
single package with no glue)(7473, 7476, ?4027 etc). While the JK flip-flops
involved were happy with lab generated signals they resolutely refused to
behave with real world generated signals (from hall sensor and/or reed
switch). The results were intermittent. Divide by 3 3 3 2 3 3 2 4 2 3 3 3 6
3 .....

I have now gone to a 4040 counter with a naughty two diode and resistor "AND
gate" to drive the reset. Resistor from RESET to Vcc. Diodes from Q1 and Q3
to RESET (Anode ends). When both outputs are high the diodes block, resistor
pulls up reset line and both Q's fall again. The resultant reset pulse is
therefore "just long enough:" to cause reset and has the potential to only
partially reset the IC. As I am using just the first two stages the chances
for erroneous operation MAY be reduced compared to higher divide ratios.

The 4040 has a Schmitt trigger clock input which cures the input rise time
problem but this circuit substitutes a potentially fatal race condition for
the JK's input rise time limitation. I can however "design" for the 4040's
behaviour across a spread of device parameters. In testing it seems
remarkably immune to improper performance and the application can in fact
stand the occasional mis-reset (even one in ten would be OK!) but I'm still
somewhat nervous about such "improper" methods. Adding a capacitor to the
reset line potentially improves operation but doe not seem necessary. Adding
a 2 stage RC filter would allow some proper reset hold time but seems even
less necessary.

Anyone want to implement a more elegant asymmetric divide by 3 on an
asymmetric 3 to 70 Hz input signal at a lower all up cost than a CD4040, 2 x
1N4148's and a 100k resistor :-) ? Best cost from another source (method
unknown) was $US1 manufacturing cost per unit in moderate volume.



       Russell McMahon

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2002\05\27@040429 by Roman Black

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Russell McMahon wrote:
{Quote hidden}

Yep. :o)
Use a 4017 decade counter, it counts out up to
10 counts, one on each pin. Often used for
"knightrider" flashing light displays etc.
Tie the third output to the reset pin, this is
a standard way to get low counts. Obviously you
can use that point to get your /3 output signal
from too. :o)
-Roman

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2002\05\27@074408 by Russell McMahon

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> > I have been asked to divide a digital signal by 3.

> > Anyone want to implement a more elegant asymmetric divide by 3 on an
> > asymmetric 3 to 70 Hz input signal at a lower all up cost than a CD4040,
2 x
{Quote hidden}

I thought about using a 4017.
Unlike the 4040 it doesn't have a Schmitt input on the clock so is more
prone to erroneous clocking in real world situations.
The 4017 clock rise & fall time are specd at 20 uS max which is far better
than the 500 Ns odd specs for JK flip flops - may work OK in many real world
apps and very likely in mine. The 4040 spec for rise and fall time is "no
limit" due to the Schmitt trigger input.

The 4017 reset method (which I have used before today) is also "naughty" in
the same manner as my 4040 method - but it does work and it saves two diodes
and a resistor.

Note that, if you use the 3rd output as your divide output you are liable to
be disappointed. The pulse here, as with the 4040, lasts only until the IC
resets and is usually VERY short and will typically not rise to anywhere
near full supply (not on my 100 MHz scope anyway :-) ) . Using either of the
other 2 outputs produces a 1/3 duty cycle output.



       Russell McMahon

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2002\05\27@080936 by Olin Lathrop

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> I have been asked to divide a digital signal by 3.

3 is an akward number.  My first reaction is to step back and take a system
wide view.  Why 3?  How is the signal being used?  Could the rest of the
system be easily modified to not require the divide or deal with a divide by
a power of 2?  Is there a programmable part elsewhere in the system that can
compensate?

{Quote hidden}

flip-flops
> involved were happy with lab generated signals they resolutely refused to
> behave with real world generated signals (from hall sensor and/or reed
> switch). The results were intermittent. Divide by 3 3 3 2 3 3 2 4 2 3 3 3
6
> 3 .....

Are there any other spare gates from the rest of the circuit?  If there are
spare inverters, these could be specified to be schmitt trigger and front
end the flip flops.  If not, 2 CMOS inverters and two resistors make a
schmitt trigger.  If there are no suitable gates, you can do it with two
transistors and a few resistors.


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2002\05\27@100437 by Russell McMahon

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> > I have been asked to divide a digital signal by 3.

> 3 is an akward number.  My first reaction is

All good thoughts.
I've tried to think of them all already - alas the situation is fairly well
constrained.

> to step back and take a system
> wide view.  Why 3?

The customer says so :-)
It's the input to a console for a piece of "rotating machinery" for a
consumer application. The speed is much faster than they are normally used
to because the equipment it's being used with is different than usual and
the sensor is on a motor pulley running at up to 4000 rpm * - usually it's
on a slower moving pulley but in this equipment there is no slower moving
wheel. The divide by 3 happens to match a standard setting in the equipment.
The processor is mask programmed and produced in zillion quantities. (*
spits magnets nicely when you use 5 minute epoxy to fasten them :-) ).

> How is the signal being used?  Could the rest of the
> system be easily modified to not require the divide or deal with a divide
by
> a power of 2?

I asked that. They are still considering if any power of 2 division will
strike some other standard ratio but the answer will probably be , "no".:

> Is there a programmable part elsewhere in the system that can
> compensate?

No. As above. Mask programmed.

> Are there any other spare gates from the rest of the circuit?  If there
are
> spare inverters, these could be specified to be schmitt trigger and front
> end the flip flops.

No spare gates.

> If not, 2 CMOS inverters and two resistors make a
> schmitt trigger.  If there are no suitable gates, you can do it with two
> transistors and a few resistors.

I built a 2 transistor Schmitt trigger to trial the result when using JK
flip flops for the divide. Haven't had to do that for a few decades :-)
Looked reasonably nice on the scope - didn't pursue it too far. The JK's
didn't like it though - better but not clean enough for 100% reliable
operation. Probably still not meeting the JK rise/fall time specs. I could
have tried to improve the Schmitt and may well have succeeded but the
component, board area and loading costs would have been in excess of the 2
diodes plus resistor required by the CD4040 solution. (2 transistors, 3+
resistors, probably a speed up cap by the time I was finished.)

The 4040 solution works with hall and reed sensors up to 4600 rpm and as
slow as I wished. Would be fun to get down to a true 1 chip solution but I
doubt it's going to happen economically. A dual JK with a Schmitt clock
would do it - but would proibably be non-standard enough to cost more
overall. Some of the programmable/presettable dividers  have beckoned but
the lack of Schmitt input makes the 4040 solution about as good.

All good fun though.



       Russell McMahon

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2002\05\27@135658 by Dwayne Reid

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>Russell McMahon wrote:
>
>  I have now gone to a 4040 counter with a naughty two diode and resistor "AND
>  gate" to drive the reset. Resistor from RESET to Vcc. Diodes from Q1 and Q3
>  to RESET (Anode ends). When both outputs are high the diodes block, resistor
>  pulls up reset line and both Q's fall again. The resultant reset pulse is
>  therefore "just long enough:" to cause reset and has the potential to only
>  partially reset the IC. As I am using just the first two stages the chances
>  for erroneous operation MAY be reduced compared to higher divide ratios.

This should be reliable.  But you can eliminate 1 diode - use the resistor
in place of the diode.  If you think about it, you wind up with the same
logic.  The pin with the resistor has to be HI before the reset can occur,
the pin with the diode also has to be HI or it is still clamping the reset
pin LO.  In other words, 1 resistor and 1 diode makes an AND gate.

dwayne

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2002\05\27@155703 by Russell McMahon

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> >  I have now gone to a 4040 counter with a naughty two diode and resistor
"AND
> >  gate" to drive the reset. Resistor from RESET to Vcc. Diodes from Q1
and Q3
> >  to RESET (Anode ends). When both outputs are high the diodes block,
resistor
> >  pulls up reset line and both Q's fall again. The resultant reset pulse
is
> >  therefore "just long enough:" to cause reset and has the potential to
only
> >  partially reset the IC. As I am using just the first two stages the
chances
> >  for erroneous operation MAY be reduced compared to higher divide
ratios.
>
> This should be reliable.  But you can eliminate 1 diode - use the resistor
> in place of the diode.  If you think about it, you wind up with the same
> logic.  The pin with the resistor has to be HI before the reset can occur,
> the pin with the diode also has to be HI or it is still clamping the reset
> pin LO.  In other words, 1 resistor and 1 diode makes an AND gate.

Aaaagh ! - brilliant (yet so obvious in retrospect).
Saves a diode (with attendant component, space, loading).
A small but worthwhile victory and I can't see that it would affect the
operation in any adverse way.
Wonder if the reset race condition becomes more marginal? Well done!


       Russell McMahon

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2002\05\28@020510 by Vasile Surducan

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On Mon, 27 May 2002, Dwayne Reid wrote:

> >Russell McMahon wrote:
> >
> >  I have now gone to a 4040 counter with a naughty two diode and resistor "AND
> >  gate" to drive the reset. Resistor from RESET to Vcc. Diodes from Q1 and Q3
> >  to RESET (Anode ends). When both outputs are high the diodes block, resistor
> >  pulls up reset line and both Q's fall again. The resultant reset pulse is
> >  therefore "just long enough:" to cause reset and has the potential to only
> >  partially reset the IC. As I am using just the first two stages the chances
> >  for erroneous operation MAY be reduced compared to higher divide ratios.
>
> This should be reliable.  But you can eliminate 1 diode - use the resistor
> in place of the diode.  If you think about it, you wind up with the same
> logic.  The pin with the resistor has to be HI before the reset can occur,
> the pin with the diode also has to be HI or it is still clamping the reset
> pin LO.  In other words, 1 resistor and 1 diode makes an AND gate.
>
> dwayne
>
 In CMOS tehnique you may use also capacitors for AND or OR as derivative
choice. The only problem is to not have trust in the input internal
protection diodes.

regards, Vasile

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2002\05\29@163036 by M. Adam Davis

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Just thinking about it.

What about a simple integrator/comparator?  It would take very few
components, and with a well defined signal could be just as reliable as
a digital system.

The pulse length is known, so charge up a capacitor each time the pules
comes along.  Trigger a comparator when the cap is three pulses full,
and the comparator also drains the cap with a transistor.

You could expand on this with a schmidt trigger or window comparator -
by designing a resistor in series with the transister you can define the
output pulse length.

Noise is just as much an issue here as with other circuits, but the
filter is built in, and if you have enough noise to make up for the
power of an additional pulse then you've got more serious problems than
dividing by three...

I imagine 4 passive components, 1 transister and an 8 pin chip.  It
could take up less space than the decade counter alone.

-Adam

Russell McMahon wrote:

{Quote hidden}

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