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'[EE]: Creating 1us pulse delay in hardware'
2001\08\29@130323 by D. Schouten

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Hi All,

I was wondering if some of you guys happen to know a simple circuit to
create a 1us (approx.) delay for a 20kHz PWM signal coming out of a
PIC. I need this to create a death-time in order to avoid current
shoot through in an H-bridge.

The circuit I have right now consists of a small RC to slow down the
ramps of the pulse, followed by a comparator with significant
hysteresis. The comparator hysteresis is set at 1/3 and 2/3 of vdd.
This circuit seems to work ok, but I was wondering if there were other
options too. Or is my current approach not so bad after all?

Thanks!

Daniel...

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2001\08\29@135920 by Herbert Graf

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Porbably overkill for what you want to do but one device I remember reading
about that does this sort of thing is a "bucket brigade" device. It is used
in audio to create echos. TTYL


> {Original Message removed}

2001\08\29@141946 by Barry Gershenfeld

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Overkill, yes, but a good idea.  The bucket brigade is made for audio
delay which means thousands of steps and analog.  Neither of which
is needed.  But the digital equivalent would be a shift register
and a clock.   With 1 MHz and two flip-flops you can get
a delay that would be 1-2 us.  If you want more resolution
just add more stages and up the clock, thus upping the "refresh"
rate.

{Quote hidden}

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2001\08\29@160227 by Dan Michaels

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At 07:02 PM 8/29/01 +0200, you wrote:
>Hi All,
>
>I was wondering if some of you guys happen to know a simple circuit to
>create a 1us (approx.) delay for a 20kHz PWM signal coming out of a
>PIC. I need this to create a death-time in order to avoid current
>shoot through in an H-bridge.
>
>The circuit I have right now consists of a small RC to slow down the
>ramps of the pulse, followed by a comparator with significant
>hysteresis. The comparator hysteresis is set at 1/3 and 2/3 of vdd.
>This circuit seems to work ok, but I was wondering if there were other
>options too. Or is my current approach not so bad after all?
>


A logic gate should also work in place of the comparator. Actually
I am surprised that simply inserting the RC in line to the h-bridge
alone does not do the job. Guess it depends upon the exact ckt.

- dan
============

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2001\08\29@171744 by D. Schouten

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Barry,
The bucket brigade solution is indeed a bit of overkill in my case.
Unfortunately a shift register plus flipflops too, however I like the
idea. The circuit I have right now only contains one comparator and a
couple of resistors/capacitors.

Dan,
You mean let the hysteresis of the input stage of the H-bridge driver
do the work? Might be a good idea, it deletes the comparator. However
I'll have to see how big the H-bridge driver's hysteresis is. If it's
too small, I will need to slow down the pulse edges too much, limiting
duty-cycle.

Thanks.

Daniel...


{Original Message removed}

2001\08\30@045317 by G. Cadman

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I don't have the begining of this message string but. It may be possible to
create this by using the propagation delay of a logic gate(s). e.g. using an
AND gate, simply connect both inputs together and your output will be your
input delayed by the propogation time.

Regards

Gary

> {Original Message removed}

2001\08\30@082818 by Alan B. Pearce

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>I don't have the begining of this message string but. It may be possible to
>create this by using the propagation delay of a logic gate(s). e.g. using
an
>AND gate, simply connect both inputs together and your output will be your
>input delayed by the propogation time.

The trouble is that he only needs the delay in the turn-on direction, it
will need to turn off immediately. The usual way to do this is with an AND
gate which has a very short RC time constant between the inputs. The input
directly connected to the control signal turns the output off immediately,
and the RC delay on the other input provides the delay that stops both
inputs going to the true state simultaneously, and hence the output is
delayed slightly before going true.

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2001\08\30@133408 by Barry Gershenfeld

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>>It may be possible to create this by using the propagation
>>delay of a logic gate(s). e.g. using an AND gate, simply
...
>The trouble is that he only needs the delay in the turn-on direction, it
>will need to turn off immediately.

Well the other problem is that gates provide delays of a few ns, so
you would need to string a LOT of them together to get up to
a microsecond.  But I suspect the RC delay as suggested is quite
good enough since the rise time of something like that is
fast enough not to be noise sensitive or require a schmitt-trigger
(though you could throw one in for good measure).

If that one-direction thing is true, that can be solved with
another gate (or with Alan's method, for minimum parts count).

Barry

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2001\08\30@141216 by D. Schouten

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Barry,
Yes, indeed you'll need a lot of gates to provide a 1us tpd.

Alan,
Your method crossed my mind too, but I didn't expect it would work
with a 20kHz PWM signal. I will at least need an antiparallel diode
across the resistor of the RC to let the capacitor discharge
immediately at low state of the PWM signal. Else, the delayed pulse on
the output of the AND gate will have the same delay at turnoff too. Or
am I missing something here?

Thanks!

Daniel...

{Original Message removed}

2001\08\31@043654 by Alan B. Pearce

face picon face
>Your method crossed my mind too, but I didn't expect it would work
>with a 20kHz PWM signal. I will at least need an antiparallel diode
>across the resistor of the RC to let the capacitor discharge
>immediately at low state of the PWM signal. Else, the delayed pulse on
>the output of the AND gate will have the same delay at turnoff too. Or
>am I missing something here?

I wonder if you really need a full 1uS, as you really only need enough time
to stop the two transistors in the totem pole from conducting
simultaneously, and with suitable gate drive they should switch faster than
this.

Let me try some ASCII art

                             -----\
 input drive ----------------|     \
                     |       |  &   \
                     R       |      /
                     +-------|     /
                     |       |----/
                     C
                     |
                  ground

now consider what happens when the input drive signal is low, the output of
the gate will be low as both inputs are low. When the input drive goes high,
one input of the gate will go high, but the other input will not go high
until the input has been high for a time determined by the RC time constant.
Therefore the output will not go high until a delay determined by RC has
occurred.

Now with the output high, when the input drive goes low, the output will go
low immediately (subject to gate delay) as one input has now gone low.
Provided the input drive stays low for a period greater than the RC time
constant the situation in the previous paragraph will hold when the drive
goes high again. As someone else mentioned it may be worth putting a diode
across the R to discharge the C when the input is low.

If you do not wish to use an RC and have spare gate packages available then
these could certainly used between the two pins as mentioned by someone
else. This is a valid technique for determining edges on wave forms by
replacing the AND gate with an XOR gate, although typically 3 or 4 gates in
series would be used for the delay in this case. The verification of this is
left to the student :)

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2001\08\31@120443 by Peter L. Peres

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Normally delay circuits using RC and gates use an AND or NAND gate that
makes sure that the delay happens only on one transition.

A simple RC or RLC delay element will delay in both directions.

Peter

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2001\08\31@120703 by Peter L. Peres

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Why didn't anyone suggest the Q=1 LC delay circuit ? A PI circuit would be
nice here.

Peter

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'[EE]: Creating 1us pulse delay in hardware'
2001\09\01@141943 by D. Schouten
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> Why didn't anyone suggest the Q=1 LC delay circuit ? A PI circuit
would be
> nice here.

Peter, is it possible to create a 1us delay with such a circuit? I
have checked socalled passive delaylines which are configured as a PI
filter, but they didn't came above 10 to 20ns.

Daniel...

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2001\09\02@174408 by Peter L. Peres

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A PI circuit with Q=1 is a form of 'all pass' filter. Basically you have a
critically damped RLC circuit, thus the phase delay is very well known. If
you follow this with an active switching element (a transistor or a gate
or a *valve*) then you get a nicely reshaped delayed edge wrt. the input
edge. A coaxial delay line does the same thing at higher frequencies. A
series critically damped RLC can be used to make a single impulse from an
edge f.ex. Some of this is used in sonar, radar and sampling (S&H)
circuits. I understand that some ground penetrating radar for scientific
applications uses something like this to make the wideband pulse. The idea
scales well and some versions are used in multi-megawatt physics
experiments to make fast pulses etc.

Peter

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