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'[EE]: 8 output pins from 1 pin hardware challenge.'
2002\05\25@085350 by Russell McMahon

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This "challenge" covers the provision of an 8 bit output port driven by a
single optically coupled digital output line. Constraints such as lowest
cost and PCB area add interest to the requirement.

I have to produce 4 to 8 digital output lines from an RS232 level "RTS"
output. (At least 4 outputs required - more would be useful). The so called
RTS line is in fact a general purpose digital output line. The client
requires the line (and an accompanying RS232 serial data line) to be
optoisolated from the target - mainly to prevent the equipment acting as an
earth path for the heavy currents drawn by the target equipment.

The final product (which has a other functions not relevant to this
"challenge") mounts inside a VHF R/T (radio telephone) immediately above the
BNC RF aerial connector. This doesn't seem to pose excessive problems in
prior versions of the application. Present final volume is moderate
(hundreds) BUT there is a prospect for a very large volume follow up
(100k?). Data transfer rate is not critical. Probably a data word sent in 10
to 100 ms when required would suffice. Faster is acceptable.
Operation from 5 volts. CMOS (wimpy) output drive levels OK.

Key design constraints are

   - lowest cost
   - smallest PCB area (within reason).
   - Doesn't affect R/T operation
   - works

The obvious solution is a UART. All that I have found fail the cost
requirement substantially when compared with alternatives.

The next most obvious is a single chip microprocessor. These too seem too
dear for the task. Even a 12C508 or 16C505 are far dearer than hardware
alternatives ($US1+)(Z8PExxx down to about $US0.90). The need for
programming adds slightly to the cost. Other brands seem hard pressed to get
under about $US1. Some of the more exotic Asian 4 bitters would probably
halve this. The anguish of pursuing this path MAY be justified for the 100K
solution, maybe.

Using the data line plus the accompanying RS232 line and implementing IIC
could be a solution. Circuitry to prevent the RS232 line burbling during
this time would add to complexity. (A matching return pair of optically
isolated data and control lines is present. It had not been expected that
these would be used in the output solution but this is a possibility. If so,
their existing functionality would have to remain. (RS232 RX and 1 digital
input).

The current "winner" is a CD4094 serial to parallel shift register plus 3
CD40106 inverters (half a pkg) plus a few R's and C's to derive clock, data
and latch signals from a single serial line. Positive going pulses are sent
from the controller. Pulses over a certain duration are seen as 1's, less
than this are 0's. (0 = nominal 1 ms high, 1 = nominal 3 ms high. Barn door
accuracy timing easily separates these. In practice 0's may be much shorter
if desired. As the data feed is interrupt driven these timings would be
used. Cessation of data for more than a certain period (say 10 ms) results
in latching of the data sent. ICs would be SOIC pkgs. Smaller not really
needed. The spare inverters will be used in other circuitry. Parts cost is
about $US0.40 (4094 + 40106/2 + glue).

This solution could be improved for the digital purists by using a local
clock and gated timing to replace the nasty analogue delays at the probable
expense of several extra ICs.

Any better ideas?



       Russell McMahon

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2002\05\25@142515 by Dwayne Reid

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At 11:37 PM 5/25/02 +1200, Russell McMahon wrote:

>The current "winner" is a CD4094 serial to parallel shift register plus 3
>CD40106 inverters (half a pkg) plus a few R's and C's to derive clock, data
>and latch signals from a single serial line. Positive going pulses are sent
>from the controller. Pulses over a certain duration are seen as 1's, less
>than this are 0's. (0 = nominal 1 ms high, 1 = nominal 3 ms high. Barn door
>accuracy timing easily separates these. In practice 0's may be much shorter
>if desired. As the data feed is interrupt driven these timings would be
>used. Cessation of data for more than a certain period (say 10 ms) results
>in latching of the data sent. ICs would be SOIC pkgs. Smaller not really
>needed. The spare inverters will be used in other circuitry. Parts cost is
>about $US0.40 (4094 + 40106/2 + glue).

Given your cost constraints, this is the way I'd do it.  I only see the
need for 2 Schmitt trigger inverters: Clk and latch inputs on the 4094
require fast edges.  You would be able to eliminate even those if you can
find a cheap SR with schmitt trigger inputs.  Higher end SRs do have those
(I'm thinking of the TPIC6x595 family) but those tend to be much more
expensive than the parts you have chosen.  You don't need a ST on the data
input to the SR - so long as the level is a solid 1 or 0 when the clk pulse
comes, the 4094 is happy.

Glue is 2 Rs, 2 Cs and 2 diodes - the diodes could be eliminated if you
were willing to ensure that the rest time between bits and bytes was long
enough to completely charge or discharge the RC delays.  I wouldn't bother
- adding the diodes costs hardly anything.

dwayne

dwayne

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2002\05\26@060220 by Roman Black

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Dwayne Reid wrote:
{Quote hidden}

I love these "cheap" challenges! I would be so daring
to suggest that you COULD do it with just one serial latch
chip (serial in parallel out shift reg) and two RC networks.
You only need one serial input line.

Longest RC time delay -> latch reset
Shorter RC time delay -> data in
No RC time delay -> clock

In theory a very long pulse will cause the latch reset,
then a very short pulse will clock in a 0 and a slightly
longer pulse will clock in a 1. You need a chip with clock
that latches on the end of the pulse, or just run an
inverted line from the start which will do the same thing,
so you are guaranteed to be able to do the clock and data
with one line and one RC network, no external inverters
needed.

You don't need the cost of the diodes as you can allow
at least one pulse width to discharge the cap each time,
you are not pressed for time.
One chip, 2R, 2C. Maybe. :o)
-Roman

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2002\05\26@212720 by Dwayne Reid

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At 07:58 PM 5/26/02 +1000, Roman Black wrote:
>Dwayne Reid wrote:
> >
> > Glue is 2 Rs, 2 Cs and 2 diodes - the diodes could be eliminated if you
> > were willing to ensure that the rest time between bits and bytes was long
> > enough to completely charge or discharge the RC delays.  I wouldn't bother
> > - adding the diodes costs hardly anything.
>
>
>I love these "cheap" challenges! I would be so daring
>to suggest that you COULD do it with just one serial latch
>chip (serial in parallel out shift reg) and two RC networks.
>You only need one serial input line.
>
>Longest RC time delay -> latch reset
>Shorter RC time delay -> data in
>No RC time delay -> clock

The problem with using just a cheap shift register is the limit on rise and
fall times on the clock inputs - most require rise and fall times to be
faster than 500 ns.  As I mentioned in my earlier post, some higher end
shift registers do have schmitt trigger inputs but those tend to cost much
more than a cheap SR (4021) and 2 sections of a hex inverter schmitt
trigger (4584 or 40106).

dwayne

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Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

Celebrating 18 years of Engineering Innovation (1984 - 2002)
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2002\05\27@013804 by Russell McMahon

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> >I love these "cheap" challenges! I would be so daring
> >to suggest that you COULD do it with just one serial latch
> >chip (serial in parallel out shift reg) and two RC networks.
> >You only need one serial input line.
> >
> >Longest RC time delay -> latch reset
> >Shorter RC time delay -> data in
> >No RC time delay -> clock
>
> The problem with using just a cheap shift register is the limit on rise
and
> fall times on the clock inputs - most require rise and fall times to be
> faster than 500 ns.  As I mentioned in my earlier post, some higher end
> shift registers do have schmitt trigger inputs but those tend to cost much
> more than a cheap SR (4021) and 2 sections of a hex inverter schmitt
> trigger (4584 or 40106).

And you better believe that the rise & fall time limits are real !!!!
I've been trying to squeeze an inverter out of an unrelated flip flop based
low cost/space design and while the JK flip-flops involved were happy with
lab generated signals they resolutely refused to behave with real world
generated signals (from hall sensor and/or reed switch). The results were
intermittent.

I'm trying to divide by 3 at lowest cost / space and have now gone to a 4040
counter and a naughty two diode and resistor "AND gate" to drive the reset.
The 4040 has a Schmitt trigger clock input which cures the input rise time
problem but this circuit substitutes a potentially fatal race condition for
the JK's input rise time limitation. I can however "design" for the 4040's
behaviour across a spread of device parameters. In testing it seems
remarkably immune to improper performance and the application can in fact
stand the occasional mis-reset (even one in ten would be OK!) but I'm still
somewhat nervous about such "improper" methods.

Hey - I think I'll put this up as another design challenge just for fun.


       Russell McMahon

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2002\05\27@035806 by Roman Black

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Dwayne Reid wrote:
{Quote hidden}

I should have made it clearer, the clock input has
NO RC filter so it does not suffer from rise time
problems. Only the data input and reset inputs have
the RC filters. :o)
-Roman

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2002\05\27@132253 by uter van ooijen & floortje hanneman

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> > >Longest RC time delay -> latch reset
> > >Shorter RC time delay -> data in
> > >No RC time delay -> clock

When I was a student and lived in a caravan I had to go to the lavatory
outside at night. I feared the door falling in the lock behind me and me out
in the cold with the key insde, so I built an electronic lock with a single
pushbutton switch. It use two 4000 series ICs (I don't remember which) and
some diodes. The one I built worekd very reliable, but I have my doubts
about reproduceability. The principle was to derive a clock from a delayed
rising edge of the input, so if the input went down quickly it would clock
in a 0, otherwise a 1. No reset, clocking in 8 data bits this way was enough
challenge. Just to be sure I hide an override button somewhere, and I also
buried a spare key. I guess I w as fit for 3-fail-safe space work even
then...

Wouter van Ooijen
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2002\05\27@135633 by Dwayne Reid

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At 05:53 PM 5/27/02 +1000, Roman Black wrote:
> >
> > The problem with using just a cheap shift register is the limit on rise and
> > fall times on the clock inputs - most require rise and fall times to be
> > faster than 500 ns.  As I mentioned in my earlier post, some higher end
> > shift registers do have schmitt trigger inputs but those tend to cost much
> > more than a cheap SR (4021) and 2 sections of a hex inverter schmitt
> > trigger (4584 or 40106).
>
>
>I should have made it clearer, the clock input has
>NO RC filter so it does not suffer from rise time
>problems. Only the data input and reset inputs have
>the RC filters. :o)

Yeah, except that Russell said that it was coming from an opto type
sensor.  Those have fairly slow rise and fall times unless they are the
more expensive types with a schmitt trigger driven output stage.  The
prudent thing to do is add the schmitt trigger inverter to the inputs that
need them: clk and latch inputs.

I just had a thought, though.  I've been thinking along the lines of a
hc595 which does have edge triggered output latch.  But we've also been
talking about the 4094 and I *think* that has a level rather than edge
triggered output latch.  I'll have to check.  If that is the case, the
schmitt trigger could be eliminated from that input.

dwayne

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Dwayne Reid   <@spam@dwaynerKILLspamspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

Celebrating 18 years of Engineering Innovation (1984 - 2002)
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2002\05\27@170658 by Peter L. Peres

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On Mon, 27 May 2002, Russell McMahon wrote:

>I'm trying to divide by 3 at lowest cost / space and have now gone to a 4040
>counter and a naughty two diode and resistor "AND gate" to drive the reset.
>The 4040 has a Schmitt trigger clock input which cures the input rise time
>problem but this circuit substitutes a potentially fatal race condition for
>the JK's input rise time limitation. I can however "design" for the 4040's
>behaviour across a spread of device parameters. In testing it seems
>remarkably immune to improper performance and the application can in fact
>stand the occasional mis-reset (even one in ten would be OK!) but I'm still
>somewhat nervous about such "improper" methods.

Add more diodes to forbid forbidden states and slow the input down with an
RC so it cannot change while the race can exist (T = 5x Tph ?).

Peter

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