At 11:28 PM 6/7/00 +0100, Brian Gregory wrote: {Quote hidden}
>In-Reply-To: <spam_OUT4.0.1.20000607112426.03837350TakeThisOuTmail.cedar.net>
>
>David VanHorn <.....dvanhornKILLspam@spam@CEDAR.NET> wrote:
>
>> >5. For a given capacitor type and package, higher capacitance will perform
>> >better. Usually the reason smaller capacitance values are used at high
>> >frequencies is that the low inductance packages are only available in low
>> >capacitance values.
>This is as if you didn't read past the first sentence.
I did.
EVEN within a package type, like SMD 1206 caps, (leadless) the higher C
values have higher internal inductance. Been there, measured that.
>The smaller values are used because it's not possible to create the larger
value caps >without larger internal inductance.
I agree completely, a theoretical 1uF capacitor (in any given package)
without internal inductance would bypass superbly from about 3 MHz through
microwaves. The lower end would depend on the impedance of the circuit
around the capacitor. Attenuation roughly (Zsystem + Zcap)/Zcap, assuming
good layout Unfortunately, I can only build circuits with real components,
which carry parasitic components in their construction.
>For one thing you can't always get the next value up or down sometimes the
>cap you';re using is the highest, or lowest value they make in that type.
IIRC, I measured 0.1, 0.01, 0.001 and 0.047, 0.0047 and 470pF in 1206.
Each had a pronounced dip in it's impedance, and the general observation
was that the dip occurred at an inverse of the value, with 0.1 at 3 MHz,
0.01 at 30, and so on.
I assumed that the results would hold for other values, but this is
probably not true for much smaller values in this package, as I expect
there is a fixed minimum inductance for any given package style, so I would
expect the results to bend away from that line in the smaller values. I
also had reservations about my fixturing at higher frequencies.
I also measured similar spreads in leaded axial glass caps, and disc
ceramics, and found that they tracked along the same lines. Apparently, the
larger packages end up at roughly the same internal inductance for a given
C. I was somewhat suprised by this, but I won't argue much with a direct
measurement.
Unfortunately, my lab notebooks from back there were lost a couple moves
ago, so all I can go on at the moment is my memory. If I get time (and if
it bugs me enough) perhaps someday I'll repeat the measurements and write
it up again. You could also make the experiment. Science works, wether
you believe in it or not.
>The end of your reply is completely irrelevant you talk about varying the
>frequency and seeing an minimum impedance. The paragraph you are responding
>to is about choosing the right capacitor for a particular job. WTF are you
>doing responding with an argument about a capacitor having a minimum
>impedance at a particular frequency.
That's my whole point.
Unless you're doing something VERY special, your system noise is not white.
It's concentrated around switching rates, and the odd harmonics thereof.
The noise is caused by the switching transients in your active devices (we
were mostly discussing chips) When a logic chip switches states, it draws
a current pulse. The pulse is difficult to measure, and not that
interesting in a single case. However, let's think about an HC04 inverting
a 1 MHz clock. I will see two million current pulses each second, and each
pulse will be fairly narrow. Fourier tells us that the spectrum will be a
series of spectral components, starting at 2 MHz, and ascending at odd
harmonics.
If you load the outputs of this HC04, then it will have to drive that load.
HC inputs are capacitors, so loading a gate with another gate causes a
higher pulse current to flow during the transition, while it charges the
gate capacitance. This is why series resistors are so effective in lowering
EMI, by limiting the magnitude of that current.
Proper bypassing means that when this chip draws these current spikes, they
come from the bypass capacitor, and not from the system bus. The system bus
refills the energy in the capacitor at a slower rate. We accomplish this by
making sure that the capacitor has it's minimum impedance at the proper
frequency, which corresponds to the dI/dT that the chip is using.
It's pretty hard to radiate at 2 MHz, and the FCC dosen't even look at
radiated noise until 30 MHz, so ideally you would want to look at the noise
spectrum at that chip, and apply the cap with the lowest impedance at the
frequency where you measure the highest noise component. Yes, it's a lot
of work, but when we make a million systems, it's well leveraged.
In a more complicated system, you'll have more noise spikes, and a harder
time determining where each is coming from. I've found empirically, that
if you bypass for the third harmonic of the fastest signal at a given chip,
this is usually a good starting point, and usually the result is a very
quiet system.
Odd duty cycles, or heavy loading on a line at a lower frequency will
produce more noise at other freqencies than what you would suspect, so when
you check for noise, you note it, and change the bypass accordingly.
Once you know where you are making the noise, then you can tailor the
bypassing to effectively supress the noise you are making. (not some other
noise you aren't making)
I have worked on systems where simply making these measurements and
REDUCING the byypass values made the difference between failing part 15
miserably, and passing easily.
Understand, this is not some theory I thought up one afternoon.
Part of my job is designing our systems so that they will pass emissions
testing.
Because proper bypassing is critical to that, I made some measurements of
how various bypass capacitors perform at different frequencies.
I've applied those observations over the last decade, in many designs, and
been able to rescue a fair number that I didn't design, by applying what I
learned.
I observed something, I formed a theory that let me make predictions about
it, and I applied those predictions in the real world succesfully. (Last I
checked, that was more or less how science worked.)
As another observation, bypassing in VHF and UHF circuits is usually done
with 1000pF or less capacitors, even when it is done with 1206 package
devices. If 0.01uF would do as well or better, then why would they not use
that? In commercial production, there is no real price difference, so they
must have some reason for requiring more values of parts to be stocked and
handled.
Perhaps I am misunderstanding what you are trying to achieve. What job are
you trying to make bypass capacitors perform?
<x-flowed>At 06:33 PM 6/7/00 -0700, Dave wrote:
> >This is as if you didn't read past the first sentence.
>
>I did.
>
>EVEN within a package type, like SMD 1206 caps, (leadless) the higher C
>values have higher internal inductance. Been there, measured that.
Yes, higher capacitance will lead to higher plate inductance. But this is
only one part of the equivalent series inductance. A (presumably) larger
part is lead inductance, since inductance in wires varies inversely to the
circumference. (This is why "fat" traces have less inductance than "thin"
traces".)
Plate inductance is proportional to plate area, so theoretically should
increase proportional to capacitance. However capacitance can be increased
without increasing plate area by putting the plates closer together and
using a higher-quality dielectric.
As I mentioned, the difference in packaging and component materials may be
much more important than capacitance in determining ESR and ESI.
Or are you indicating that your experience showed that high-Q,
high-dielectric and all other types of capacitors at the same capacitance
value performed the same at all frequencies? If so, you will understand I
find that hard to believe. The "laws of physics" say otherwise. For
example, ESR is determined by the dielectric dissipation, not by the
capacitance.
> >For one thing you can't always get the next value up or down sometimes the
> >cap you';re using is the highest, or lowest value they make in that type.
>
>IIRC, I measured 0.1, 0.01, 0.001 and 0.047, 0.0047 and 470pF in 1206.
>Each had a pronounced dip in it's impedance, and the general observation
>was that the dip occurred at an inverse of the value, with 0.1 at 3 MHz,
>0.01 at 30, and so on.
What types of capacitors where these? Were they all from the same parts
family? Were they SMT? If so, the lead inductance might be very small, so
your argument that plate inductance is dominant would follow.
>I also measured similar spreads in leaded axial glass caps, and disc
>ceramics, and found that they tracked along the same lines. Apparently, the
>larger packages end up at roughly the same internal inductance for a given
>C. I was somewhat suprised by this, but I won't argue much with a direct
>measurement.
This empirical observation is interesting.
What did you use for a test circuit? How did you control the effect of
layout inductance?
>That's my whole point.
>Unless you're doing something VERY special, your system noise is not white.
>It's concentrated around switching rates, and the odd harmonics thereof.
>The noise is caused by the switching transients in your active devices (we
>were mostly discussing chips) When a logic chip switches states, it draws
>a current pulse. The pulse is difficult to measure, and not that
>interesting in a single case. However, let's think about an HC04 inverting
>a 1 MHz clock. I will see two million current pulses each second, and each
>pulse will be fairly narrow. Fourier tells us that the spectrum will be a
>series of spectral components, starting at 2 MHz, and ascending at odd
>harmonics.
Yes, but these harmonics fall off at 1/f and the capacitor impedance
increases as 1/f from inductance. So to a first approximation the two
effects cancel.
>Proper bypassing means that when this chip draws these current spikes, they
>come from the bypass capacitor, and not from the system bus. The system bus
>refills the energy in the capacitor at a slower rate. We accomplish this by
>making sure that the capacitor has it's minimum impedance at the proper
>frequency, which corresponds to the dI/dT that the chip is using.
More properly you are concerned with dV/dI (ripple) at the worst-case
frequency.
>In a more complicated system, you'll have more noise spikes, and a harder
>time determining where each is coming from. I've found empirically, that
>if you bypass for the third harmonic of the fastest signal at a given chip,
>this is usually a good starting point, and usually the result is a very
>quiet system.
This certainly is true, although you don't mention the fundamental which is
the largest effect.
The object of all of this is to provide a clean waveform at the power
terminals of the chip. Any capacitor which accomplishes this at worst-case
conditions is satisfactory.
Oddly, there has been no mention of the performance requirement for this
bypassing, except my comment that the impedance should be < 1 ohm to give <
0.1 V ripple at the clock frequency (to 3rd harmonic, if you wish). No
matter what kind of capacitor is used, you will find it tough to do much
better than 0.1 ohm.
If you don't have a testable performance requirement, how do you know when
your design is complete and whether it will work in the application?
What would be really nice here is to have some equivalent circuit
parameters for real capacitors of different types in some test circuit
situation. Unfortunately, I have searched in vain for this information from
parts manufacturers. Probably because the parameters vary with the exact
application.
================================================================
Robert A. LaBudde, PhD, PAS, Dpl. ACAFS e-mail: ralKILLspamlcfltd.com
Least Cost Formulations, Ltd. URL: http://lcfltd.com/
824 Timberlake Drive Tel: 757-467-0954
Virginia Beach, VA 23464-3239 Fax: 757-467-2947
"Vere scire est per causas scire"
================================================================
>Or are you indicating that your experience showed that high-Q,
>high-dielectric and all other types of capacitors at the same capacitance
>value performed the same at all frequencies?
No, I didn't test that broad a spread of types, but I would expect each
type to show a similar behaviour, if at a different frequency per value.
>What did you use for a test circuit? How did you control the effect of
>layout inductance?
100 mil tracks over ground plane on 0.062 FR4 (50 ohms-ish)
Source on one end of the track, and measuring at the cap.
Track length, IIRC an inch or two.
>Yes, but these harmonics fall off at 1/f and the capacitor impedance
>increases as 1/f from inductance. So to a first approximation the two
>effects cancel.
The Zl seems pretty small up to a point.
>This certainly is true, although you don't mention the fundamental which is
>the largest effect.
??? With large resistive loads maybe, but cmos inputs are capacitors, so
the gate draws almost no current at the fundamental, unless it's high
enough to make the gate C low Z
>Oddly, there has been no mention of the performance requirement for this
>bypassing, except my comment that the impedance should be < 1 ohm to give <
>0.1 V ripple at the clock frequency (to 3rd harmonic, if you wish). No
>matter what kind of capacitor is used, you will find it tough to do much
>better than 0.1 ohm.
Obviously you'd like the Z to be as low as possible. Since you have a Z
that varies over F, to a minimum, and goes back up past a certain point, it
makes sense to me, to pick the valley to correspond to the highest observed
noise (presumably where you need the low Z the most)
>If you don't have a testable performance requirement, how do you know when
>your design is complete and whether it will work in the application?
"must pass part 15" works for me in terms of emi.
I don't know if anyone specs anything on logic or processors other than the
usual tolerance band around a nominal VCC. Obviously if you're driving
such heavy loads that you have observable glitches in VCC that approach the
limits, then you need to address that. (reduce load, add bypassing) Still,
you should be able to select the best bypass by looking at the width of the
glitches.
>What would be really nice here is to have some equivalent circuit
>parameters for real capacitors of different types in some test circuit
>situation. Unfortunately, I have searched in vain for this information from
>parts manufacturers. Probably because the parameters vary with the exact
>application.
I've never seen anything much except for electrolytics. There may be some
brands/types of smaller caps that have more complete specs, but not in my
inventory :(
<x-flowed>At 02:01 AM 6/8/00 -0700, Dave wrote:
> >Or are you indicating that your experience showed that high-Q,
> >high-dielectric and all other types of capacitors at the same capacitance
> >value performed the same at all frequencies?
>
>No, I didn't test that broad a spread of types, but I would expect each
>type to show a similar behaviour, if at a different frequency per value.
I think it's clear we aren't disagreeing to any significant extent anymore.
I think most of the confusion arose from you dealing with surface mount
parts and I thinking of parts with significant lead inductance.
We are still left with the fact that the resonant frequency of a capacitor
is a fixed parameter for the part and cannot be moved. Therefore we can't
assume that it's going to solve our bypass problems unless our clock
frequency and harmonics happen to accidentally coincide with the part
impedance spectrum notches.
A ceramic is higher Q than a tantalum. This means the notch goes lower in
ohms, but also is sharper in frequency. The usual range for a capacitor in
typical bypassing is the frequency band over which its impedance is 1 ohm
or less.
The impedance at frequencies lower than the notch is governed by the
capacitance value: as it goes up, the impedance goes down.
The impedance at frequencies above the notch is governed by the inductance
value: as the capacitance goes up or lead length increases the impedance
goes up.
Based on the spec graph I provided, if the performance requirement is 1 ohm
impedance or less over the widest frequency range, the tantalum 1 uF
capacitor is superior to the ceramic 1 uF capacitor. It's bandpass is 200
kHz to 20 MHz, while the ceramic is only 200 kHz to 4.5 MHz. The 0.1 uF
high-dielectric ceramic has a 1-ohm bandpass of only 1 MHz to 13 MHz. The 1
nF film ceramic has a bandpass of 100 MHz to 1 GHz.
Interestingly, the smaller ceramics have sharp notches because they have
MORE inductance than the tantalums, not LESS. What they appear to have less
of is equivalent series resistance, which leads to high Q at the notch. The
higher inductance leads to higher rise in impedance post-notch.
Consequently a tantalum has higher bandwidth, but the ceramics have lower
impedance at the notch frequency.
Again, it seems to me from this "data" that a 1 uF tantalum is superior in
bypassing than 0.1 uF - 1.0 uF ceramics up to about 20 MHz. Above that
frequency, a parallel 0.01 uF ceramic might be useful in parallel.
To go any further with this, we need some hard data or good specifications.
Dave's experience seems consistent with the results obtained for ceramics
of different values.
================================================================
Robert A. LaBudde, PhD, PAS, Dpl. ACAFS e-mail: .....ralKILLspam.....lcfltd.com
Least Cost Formulations, Ltd. URL: http://lcfltd.com/
824 Timberlake Drive Tel: 757-467-0954
Virginia Beach, VA 23464-3239 Fax: 757-467-2947
"Vere scire est per causas scire"
================================================================
> We are still left with the fact that the resonant frequency of a
> capacitor is a fixed parameter for the part and cannot be move.
What has resonant frequency got to do with it, anyway? I thought
resonance would come into play when you're trying to amplify a signal
at a particular frequency, not when you're trying to supress it?
Sure, you want the time contant of the RLC system to be small compared
to the times of your switching transients (otherwise, it'd be
equivilent to your bypass cap not having a chance to recharge before
the next current spike is required), but I don't see the advantage of
being actually NEAR a resonant frequency. Aren't you really hoping
for a a series of overdamped step responses?
At 11:39 PM 6/8/00 -0700, William Chops Westfield wrote:
>> We are still left with the fact that the resonant frequency of a
>> capacitor is a fixed parameter for the part and cannot be move.
>
>What has resonant frequency got to do with it, anyway?
Damifino.
- --
Are you an ISP? Tired of spam? http://www.spamwhack.com A pre-emptive strike against spam!
The 'resonant frequency' is a result of the capacitor's
value and the 'parasitic' or 'series' lead (wire) inductance.
Nature respects these factors and renders up a corresponding
'series resonant frequence'.
Using these 'naturally occuring' factors at RF frequencies has
been a mainstay of design in years past (when 'leaded' ceramic
disc caps or dipped mica caps were predominant) - this is not
so desireable a factor when the intent is to bypass a wide range
of 'frequencies' to ground as in logic 'bypass' caps.
>> We are still left with the fact that the resonant frequency of a
>> capacitor is a fixed parameter for the part and cannot be move.
>
>What has resonant frequency got to do with it, anyway? I thought
>resonance would come into play when you're trying to amplify a signal
>at a particular frequency, not when you're trying to supress it?
>Sure, you want the time contant of the RLC system to be small compared
>to the times of your switching transients (otherwise, it'd be
>equivilent to your bypass cap not having a chance to recharge before
>the next current spike is required), but I don't see the advantage of
>being actually NEAR a resonant frequency. Aren't you really hoping
>for a a series of overdamped step responses?
Having the bypass capacitor at series resonance can be very useful, because:
- A pure capacitor will have a reactance ( impedance ) inversely
proportional to frequency.
- A real capacitor has inductance and series resistance and shunt
resistance.
- The latter two are usually able to be neglected for decoupling purposes.
- The inductance often can not be. Inductance comes both from the leads and
from the internal construction of the part so will vary with technology to
some extent.
- As frequency increases there will be a point where the inductive reactance
is equal and opposite in sign to the capacitive reactance - ie series
resonance - at this point the capacitor will have notionally zero impedance
and be a perfect decoupling capacitor apart from the resistive component.
Both below AND ABOVE this frequency the impedance of the capacitor will
increase.
- In practice the situation will be complicated by the capacitor insisting
on appearing as a complex multi-element network aka a bandpass filter (or
several connected together) :-)
- For practical purposes, if a capacitor is operated at it's series resonant
frequency it will act optimally as a bypass capacitor.
As I noted in a post on this thread on June 6th -
"ARRL handbook gives these figures for series resonance (optimum bypassing)
for disk ceramics with total lead lengths of 0.5 inch.
part 0 5593 bytes The resonant frequency of the capacitor is the key to everything!
Remember the discussion started with what kind of capacitor was best for
power bypassing on digital chips (e.g., PIC microcontrollers).
If capacitance were the only issue, then the bigger the capacitance, the
better the regulation. This is why large capacitors are used in the inputs
of voltage regulators. The only limit on too large a capacitor would be the
effect of causing the regulator voltage to come up slow, eventually not
meeting the PIC's start time requirements.
Given we have DC/low frequency voltage regulation, we next need to remove
RF noise from the PIC power inputs. This is normally generated by switching
at the PIC clock speed or a harmonic. As Dave has indicated, the 3-rd
harmonic is the next one of importance generated by the clock square-wave.
However, the 2nd-harmonic may also occur due to internal switching in the
PIC ALU microprogram. The power in these harmonics drops off at least
inversely proportion to frequency.
To bypass 0.1 V "ripple" on the 100 mA max current the PIC can draw, we
need a capacitor impedance of 1 ohm (= 0.1/0.1) maximum. Therein lies the rub.
To get a 1 ohm impedance at 20 MHz requires a capacitance of
X(C) = 1/ (2 pi f C) => C = 1/(2 pi f X(C))
C=8 nF. So a bypass capacitor of 0.01 uF or 0.1 uF should work.
The problem is lead+sheet inductance and equivalent series resistance of
capacitors at high frequencies and having enough capacitance to filter at
lower frequencies.
The actual amplitude of the impedance of the capacitor is given by a
first-order approximation of:
Z(C)^2 = R^2 + [X(L) - X(C)]^2
where R = ESR (equivalent series resistance), L= ESI (equivalent series
inductance).
Since both capacitance and inductance are involved, there is a series
resonant frequency at which X(L)=X(C) and the impedance is a minimum at Z(C)=R.
For example, the 1 uF tantalum capacitor shown in the figure attached can
be completely characterized by the equivalent circuit impedance using
This capacitor has a 1 ohm or less impedance from 1.1 to 20 MHz.
The parameters tabulated in the attached table pretty much exactly
reproduce the curves shown in the attached figure. The exception is the 1
nF film capacitor where the "notch" is wider than expected, probably due to
resonances in the dielectric due to anomalous dispersion at very high
frequencies. The parameters stated are pretty much determined solely by the
capacitance and the impedance at f(res).
Some final comments:
1. Lead inductance is proportional to lead length, typically about 0.02 uH
per inch (0.51 uH per mm). Smaller diameter wires have higher inductance.
Lead inductance is usually the dominant term in leaded capacitors.
2. Internal inductance increases as the square-root of capacitance, not
proportional to it, as some have said here. The capacitance rises with
area, the inductance with length.
3. Electrolytic capacitors have too high ESR and ESI to provide bypassing
at frequencies above 100 kHz or so.
4. Tantalum capacitors have 1/3 the ESI of ceramic capacitors, but higher
ESR. This fact means that a 1 uF tantalum has a BETTER bypassing bandwidth
than either a 1 uF or 0.1 uF ceramic.
5. ESI of the capacitor is supplemented by ESI of the PCB traces, etc., in
a practical application. This further limits the upper frequency impedance
of the capacitor.
6. Two capacitors in parallel will exhibit superior performance to a single
capacitor of the combined value.
7. The ESR is frequency dependent at very high frequencies. This is due to
resonances present in the dielectric.
Conclusions:
1. A 0.22uF - 1.0 uF tantalum capacitor will bypass a PIC just as well or
better than a 0.1 uF ceramic.
2. Start the bypass design by selecting the impedance required based solely
on capacitive reactance. If you've got to depend on knowing the effect of
ESI of the part and the traces, you've lost the design battle!
3. Observe the power terminal waveform or an output pin oscillation. Once
the noise is removed and the square-wave is sharp, you're done.
4. Bypassing the larger capacitor with a much smaller one (e.g., 0.01 uF)
is only necessary when significant high frequency (> 20 MHz) noise is
present. This also usually means you've got other problems in your design.
The key for me in understanding all this was defining the performance
requirement (here, 1 ohm or less impedance). As usual, once you define
requirements, top-down design becomes almost trivial.
Having validated equivalent circuit models now means I can simulate the
response of any combination network using MicroSim and generate Bode plots
for the results.
</x-flowed>
Attachment converted: creation:capacitor impedance vs freq.g 1 (GIFf/JVWR) (000163F2)
<x-flowed>================================================================
Robert A. LaBudde, PhD, PAS, Dpl. ACAFS e-mail: EraseMEralspam_OUTTakeThisOuTlcfltd.com
Least Cost Formulations, Ltd. URL: http://lcfltd.com/
824 Timberlake Drive Tel: 757-467-0954
Virginia Beach, VA 23464-3239 Fax: 757-467-2947
"Vere scire est per causas scire"
================================================================
</x-flowed>
> Given we have DC/low frequency voltage regulation, we next need to remove
> RF noise from the PIC power inputs. This is normally generated by switching
> at the PIC clock speed or a harmonic. As Dave has indicated, the 3-rd
> harmonic is the next one of importance generated by the clock square-wave.
> However, the 2nd-harmonic may also occur due to internal switching in the
> PIC ALU microprogram. The power in these harmonics drops off at least
> inversely proportion to frequency.
[ Very good description of how to read capacitor specs snipped above &
below ]
There is one erroneous assumption though.
The clock frequency (and it's harmonics) aren't the main culprit you
are trying to supress. The RF noise etc is generated by the switching
transients which are of a much higher frequency and being close to an
impulse have lots of harmonics. The resulting spectrum is then
effectively modulated by the clock frequency.
So the basis of your calculations should be 1 / (rise/fall time)
rather than the clock frequency.
If you want some empirical proof (and have the gear to measure it),
build a counter using HC logic and then replace the logic with AC
parts. Keeping the clock frequency the same, compare the emissions of
the two. It's quite marked.
Steve.
======================================================
Steve Baldwin Electronic Product Design
TLA Microsystems Ltd Microcontroller Specialists
PO Box 15-680, New Lynn http://www.tla.co.nz
Auckland, New Zealand ph +64 9 820-2221
email: stevebspam_OUTtla.co.nz fax +64 9 820-1929
======================================================
<x-flowed>At 02:15 PM 6/11/00 +1200, Steve wrote:
>There is one erroneous assumption though.
>The clock frequency (and it's harmonics) aren't the main culprit you
>are trying to supress. The RF noise etc is generated by the switching
>transients which are of a much higher frequency and being close to an
>impulse have lots of harmonics. The resulting spectrum is then
>effectively modulated by the clock frequency.
>
>So the basis of your calculations should be 1 / (rise/fall time)
>rather than the clock frequency.
>
>If you want some empirical proof (and have the gear to measure it),
>build a counter using HC logic and then replace the logic with AC
>parts. Keeping the clock frequency the same, compare the emissions of
>the two. It's quite marked.
The current impulses related to current surges at switching points is
usually a much smaller effect in CMOS circuits.
Taking the PIC microcontroller as the target, we want
C = I x t / V
If I=100mA and V=100 mV as before, and t = 50 ns, then
C = 0.1x50ns/0.1 = 50 nF
In addition, if we reason the impulses are going to be short duty cycle
(not 100%), then a more reasonable value for C might be
C = 50 nF x 10-20% = 5-10 nF
So we don't need much capacitance to fix this problem.
But you are correct that the fix to this problem would have to operate
correctly at higher frequencies.
However, this problem would show up easily as ringing on the signal
transitions. So it's still true that if the signal looks clean and sharp in
the time domain, the problem is solved.
================================================================
Robert A. LaBudde, PhD, PAS, Dpl. ACAFS e-mail: @spam@ralKILLspamlcfltd.com
Least Cost Formulations, Ltd. URL: http://lcfltd.com/
824 Timberlake Drive Tel: 757-467-0954
Virginia Beach, VA 23464-3239 Fax: 757-467-2947
"Vere scire est per causas scire"
================================================================
> The current impulses related to current surges at switching points is
> usually a much smaller effect in CMOS circuits.
I would have to disagree with that. At all times other than during
switching, there is no current flowing. Switching here means between
steady state conditions so it includes trace capacitance etc.
Supplying the current during switching is the whole point of the
decoupling caps.
> So we don't need much capacitance to fix this problem.
No argument with that. Otherwise we'd be back at square one.
> However, this problem would show up easily as ringing on the signal
> transitions. So it's still true that if the signal looks clean and sharp in
> the time domain, the problem is solved.
No. The opposite. If you had no available capacitance on the supply
then the current would have to be sourced from a long way away. That
would mean that the output of the pin would appear to rise slowly. At
the same time, the supply (local to the chip) is going to be pulled
down (and the ground pin, up) because of the loading. It is the
supply that shows the ringing and it is quite apparent on a scope.
Steve.
======================================================
Steve Baldwin Electronic Product Design
TLA Microsystems Ltd Microcontroller Specialists
PO Box 15-680, New Lynn http://www.tla.co.nz
Auckland, New Zealand ph +64 9 820-2221
email: KILLspamstevebKILLspamtla.co.nz fax +64 9 820-1929
======================================================
> The current impulses related to current surges at switching points is
> usually a much smaller effect in CMOS circuits.
I would have to disagree with that. At all times other than during
switching, there is no current flowing. Switching here means between
steady state conditions so it includes trace capacitance etc.
Supplying the current during switching is the whole point of the
decoupling caps.
> So we don't need much capacitance to fix this problem.
No argument with that. Otherwise we'd be back at square one.
> However, this problem would show up easily as ringing on the signal
> transitions. So it's still true that if the signal looks clean and sharp in
> the time domain, the problem is solved.
No. The opposite. If you had no available capacitance on the supply
then the current would have to be sourced from a long way away. That
would mean that the output of the pin would appear to rise slowly. At
the same time, the supply (local to the chip) is going to be pulled
down (and the ground pin, up) because of the loading. It is the
supply that shows the ringing and it is quite apparent on a scope.
Steve.
======================================================
Steve Baldwin Electronic Product Design
TLA Microsystems Ltd Microcontroller Specialists
PO Box 15-680, New Lynn http://www.tla.co.nz
Auckland, New Zealand ph +64 9 820-2221
email: RemoveMEstevebTakeThisOuTtla.co.nz fax +64 9 820-1929
======================================================
<x-flowed>At 02:15 PM 6/11/00 +1200, Steve wrote:
>There is one erroneous assumption though.
>The clock frequency (and it's harmonics) aren't the main culprit you
>are trying to supress. The RF noise etc is generated by the switching
>transients which are of a much higher frequency and being close to an
>impulse have lots of harmonics. The resulting spectrum is then
>effectively modulated by the clock frequency.
>
>So the basis of your calculations should be 1 / (rise/fall time)
>rather than the clock frequency.
>
>If you want some empirical proof (and have the gear to measure it),
>build a counter using HC logic and then replace the logic with AC
>parts. Keeping the clock frequency the same, compare the emissions of
>the two. It's quite marked.
The current impulses related to current surges at switching points is
usually a much smaller effect in CMOS circuits.
Taking the PIC microcontroller as the target, we want
C = I x t / V
If I=100mA and V=100 mV as before, and t = 50 ns, then
C = 0.1x50ns/0.1 = 50 nF
In addition, if we reason the impulses are going to be short duty cycle
(not 100%), then a more reasonable value for C might be
C = 50 nF x 10-20% = 5-10 nF
So we don't need much capacitance to fix this problem.
But you are correct that the fix to this problem would have to operate
correctly at higher frequencies.
However, this problem would show up easily as ringing on the signal
transitions. So it's still true that if the signal looks clean and sharp in
the time domain, the problem is solved.
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