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'[AVR]: ADC problem, somewhat mysterious at this po'
2004\10\16@175058 by Dave VanHorn

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I'm thinking this through aloud, trying to figure why a T26 ADC is giving
me a way lower value than I expect.

This is a dynamic situation, I can't easily make steady state measurements.
In a particular combination of external factors, the ADC is giving me
apparently "insane" outputs.

VCC and AVCC measure 4.29V
AREF is external, measures 2.469V
Input voltages measure 2.199V and 2.129V (70mV differential)
ADCSR is loaded with 86h Enabled, CK/64
T26 is running from the 8 MHz RC osc
125kHz ADC clock, well within spec.

I'm measuring differential inputs on channels 1/0 differentially.
I load ADMUX with 4Bh  Differential, Gain=20 Ch0 high, CH1 low
I wait 10mS (spec says at least 125uS after channel change)
Then I start a conversion
I wait for the conversion flag.
I read the ADC regs in low/high order.

With the voltages specified, and the formula from the data book, I get this:
ADC = ((Vhi-Vlo)*20*1024) / 2.469
and ADC should then read 244h  which is about what the software is expecting.

What I get looks like about 082h or thereabouts. Unfortunately the system
is running at this point, and I can't take a "snapshot" of voltage and the
ADC reading at any instant to verify absolutely.  The ADC output does vary
with the input, and this isn't a simple case of broken hardware/avr.

I've scoped the inputs, and there's no significant noise. They are R/C
filtered pretty well.

I've verified that the channels are connected where I think they are.
(again, this only acts up with specific but as yet unquantified values of
input voltage and impedance)

So, the inputs are not above Vref or VCC, or AVCC, nor even near it.
As far as I can tell, I'm setting up the ADC correctly.
This is an old system, and old code that has been working ok. No recent
changes to the code.

Other channels (not differential) are reading correctly, and are done by
the same routines.  The only major difference is using the differential
mode, and that this particular measurement is delayed to sync up with other
events that the processor controls.

There is no way that the inputs are really as low as the ADC is telling me
that they are, when I make the measurement.

I added some code to take an I/O pin high while I'm making this
measurement, and verified on the scope that the input voltage isn't doing
anything significant at this time.
The scoped voltages during the sample are within 5% of where I think they
should be, but the ADC output is WAY off.



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2004\10\17@173509 by Dave VanHorn

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Problem solved.

Somehow, the pullups on portA have been enabled.
This forces current into the ADC pins along with the sensing input, and
pushes them up near, and past, Aref.  When this happens, the ADC output
drops to near zero.

I checked the LST file, and I don't see anywhere where those pullups get
turned on, and I DO see an explicit turnoff in the init code, but disabling
the pullups right before the ADC measurement solved the problem.

I'm not sure why they allow pullups when the ADC is enabled, but they do..
 

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