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'=?Iso-8859-1?Q?Re:_[PIC]:_Please_help_!,_retfie_fa'
2001\02\21@075101 by o-8859-1?Q?K=FCbek_Tony?=

flavicon
face
Hi,

Andrej wrote:
>Hi Tony,
>
>on HiTech PicC18 repotred bugs page:
>
>NOP instructions have been inserted after TBLRD instructions. This has
fixed
>a reported problem with TBLRD instructions in silicon. This phenomenom is
>undocumented and does not appear to occur under emulation. Until this
matter
>can be resolved NOP instructions will be placed after TBLRD instruction by
>the code generator.
>
>Try to put NOP's after TBLRD.
>
>Andrej

THANK YOU, THANK YOU, THANK YOU.... :)

That did it, even managed to get the isr to fire at the
same location ( after adding a few nop's ) and it seems
to work now.

BTW the statement 'does not appear to occur under emulation'
is incorrect, I found it during emulation with ICE2000 and
PCM18XA0. However a very 'picky' bug as it seems to require
several factors at the same time.

Makes me wonder though, how many more bug's ( that are not
caused be me :-) ) are still there....hmmmm..

I think this was the first undocumented ( at least to my knowledge )
'silicon' bug I've encountered. But found two in mplab during the last
month.

How many left ? any guesses ?

Did I say thank you ?

/Tony






Tony Kübek, Flintab AB            
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2001\02\21@090634 by o-8859-1?Q?K=FCbek_Tony?=

flavicon
face
Hi again,
I forgot to mention that the bug never occured when
stepping, *only* when running at full speed.
Which made it a bit 'nasty' to nail down.

But thanks to the complex triggers :) it soon
surfaced.

/Tony



Tony Kübek, Flintab AB            
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E-mail: .....tony.kubekKILLspamspam@spam@flintab.com
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