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''509, '509JW and '509A mysteries'
1999\04\29@092731 by robert a. moeser

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hi!

i followed the recent traffic on the unfortunate matter of the '509A as
i was having some very unusual problems debugging a circuit using two
'509s.

i developed most of it using two '84s. i got it working quite well and
started moving it to the '509, using two JW parts.

the programs, which communicate by a simple protocol i devised, did not
work nearly as well. it seemed to be a matter of timing, or something.

i went back to using the '84s, and then prayed and burned two new '509A
OTP parts. the two function perfectly together.

but using a JW part as the either other PIC (or both) would not work.

CURIOUSLY i accidently removed a 0.1uF capacitor from the breadboard and
an odd couple started to work perfectly.

this seemed backwards and troubled me greatly.

i took the test code posted recently and played with it a bit. on the
'84 at 4MHz, the program generates a 3937 Hz square wave.

i was measuring the JW frequency with a similar program when i realized
i still had the '84 on the breadboard ticking away at 3937 Hz.

one JW part ran at 3939 with the '84 running beside it, but cooled down
to 3888 when it was all alone.

so... it seems that the two processors can affect each the other's
clock. and i had an explanation for the capacitor.., without it, the two
PICs could "synchronize" due to power supply coupling. hence the
programs would run at the same speed and cooperate well. with the
capacitor, the two PICs each could take on a "natural" frequency, and my
scheme would break.

sadly, even this does not explain my difficulties, as the greatest speed
difference observed was about 2 percent, and my protocol should be way
more tolerant: it is basically a PW thing, using pulses of 12 uS (SHORT)
and 36 uS (LONG) which the receiving PIC busy-waits for edges (with 3 uS
tolerance) and samples at the 24 uS (SAMPLE) mark.

works so well with two '84s or two OTP '509As. bwa bwa bwa wha wha
wawawa.

oh, just for the hell of it i burned one OTP '509A with the test program
and got a fine 3938 Hz result.

-- rob

1999\04\29@104501 by Barry King

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face
Robert,

If I have this straight- only the '509 JWs show the problem?

Do you have the windows covered on the JWs?  Weird things happen to
CMOS logic when irradiated.  Even by room light.

Any help?

------------
Barry King, KA1NLH
Engineering Manager
NRG Systems "Measuring the Wind's Energy"
Hinesburg, Vermont, USA
spam_OUTbarryTakeThisOuTspamnrgsystems.com
"The witty saying has been deleted due to limited EPROM space"

1999\04\29@121517 by Dan Larson

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On Thu, 29 Apr 1999 08:26:52 -0500, robert a. moeser wrote:

[SNIP]
>
>i was measuring the JW frequency with a similar program when i realized
>i still had the '84 on the breadboard ticking away at 3937 Hz.
>
>one JW part ran at 3939 with the '84 running beside it, but cooled down
>to 3888 when it was all alone.
>
>so... it seems that the two processors can affect each the other's
>clock. and i had an explanation for the capacitor.., without it, the two
>PICs could "synchronize" due to power supply coupling. hence the
>programs would run at the same speed and cooperate well. with the
>capacitor, the two PICs each could take on a "natural" frequency, and my
>scheme would break.
>

PLL = "PIC Locked Loop" !?!?

Dan

1999\04\29@194858 by Richard Prosser

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Sorry - I haven't caught all the previous traffic on this thread - but one
comment you made below stands out.
The new improved system worked ok without the 100n bypass right!
This indicates to me that the bypassing is not working too well. Now,
capacitors are not perfect and PCB tracks have a certain inductance also
(0.5-1nH/mm is a commonly quoted figure).
If you simulate using Pspice (etc.) a real PCB bypass situation, using
realistic models for track inductance, capacitance inductance and esr etc
then you can see some pretty powerful resonances even down in the frequency
band below 100MHz. If these correspond to a clock harmonic or can be excited
by fast risetime pulses then all sorts of things can happen.
The trick is not to use higher bypass values than is required (normally 10nF
will do)and provide as much PCB power plane track capacitance as possible.
This capacitance (say 1nF) will typically have very low series inductance.
If you feel you must use higher value bypass caps (100nF) then look at
adding a small amount of resistance in series to damp out any resonances
that do occur. 1 ohm might be a good starting point.
If you have access to a signal generator and network analyser or rf
impedance meter you can look at the resonances more directly. You might be
surprised by the result.

hope this assists

Richard Prosser

{Original Message removed}

1999\04\29@205759 by Mike Keitz

picon face
On Thu, 29 Apr 1999 08:26:52 -0500 "robert a. moeser" <.....ramKILLspamspam@spam@TIAC.NET>
writes:

>so... it seems that the two processors can affect each the other's
>clock. and i had an explanation for the capacitor.., without it, the
>two
>PICs could "synchronize" due to power supply coupling.

That's entirely possible, though of course you can't depend on it
happening.  The protocol you describe should have a large tolerance for
clock speed mismatch.  Perhaps there is a bug in the implementation, it
so it actually needs the speeds to match.  Try testing on F84's with
deliberately different crystals.  Using 4.00 MHz and 3.58 MHz should be a
good approximation of the worst case difference between two 12C509's.

Programs can also fail on JW parts because light coming in the window
causes them to operate differently.  If the light is weak, it will
probably only cause the RAM locations to be different at power-on.
Unless your software is defective, that shouldn't matter.  Strong light
can cause the PIC to malfunction.  Cover the window during tests.  Also
JW parts will give uncertain results if they haven't been fully erased.
Bits in the program memory that should have been erased to 1 will revert
back to 0, especially at low voltage.

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