Re: [EE] scope project anyone? (from PICLIST) FW & Drive cases by "Alan B. Pearce" .

>> If you're talking l/a trigging, the design for that is well known.

>> LATCH, XOR and AND into wired or. You have one latch for level and

>> one for don't care.

>

>    Um, wouldn't it be easier to just dynamically reconfigure your

>    FPGA, reprogramming it on the fly for whatever trigger pattern

>    was desired?

I remember an article in HP journal a good few years ago about how they

implemented a fast trigger recognition system in a logic analyser. Basically

they used a number of fast bipolar ram chips (well I did say it was a good

few years ago) and loaded them with the required trigger pattern. Then the

address lines were connected to the logic inputs to sense the state. This

method requires a one bit wide ram. For expansion to more bits, add another

ram and AND/OR the outputs as appropriate. Minimises propagation delay down

a tree of ORing/ANDing gates.

Could probably find the article in my archives somewhere if it might be

useful.

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