piclist 2002\09\11\030457a >
Thread: AUVic needs help from EE with Motor Control Experience
www.piclist.com/techref/io/motors.htm?key=motor
BY : Donovan Parks email (remove spam text)

Thanks for the detailed calculations.  It will take me a few days to digest
this, but I'm sure I'll have a few questions at that time.  Can you
recommend any books and/or links that may help me understand some of this
information?  Thanks.

Regards,
Donovan Parks

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that
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the
> right heat sink given the amount of power you want to dissipate. In order
> to figure out if the FET, and your FET driver will do the job look at a
> single switching sequence.
> (1) Let us look at the point when the top FET in one leg and the bottom
FET
> in the other leg have been conducting.
> (2) Your input waveform now transitions from say high to low for the top
> leg. The input waveform for the bottom leg will still be low if you have a
> deadtime built into the system to prevent shoot through. The drain current
> in the TOP FET of one leg now starts to fall with a rate of Di/Dt. This
> induces a voltage of magnitude Ldi/dt where L is the inductance of your
> motor winding at the center of the leg. As soon as the voltage at the
> center of the leg reaches one diode drop below the body diode of the
bottom
> FET of the same leg, the load current will be supported by the body diode
> of the bottom FET.
> (3) After the deadtime is up, the Top FET of the other leg is turned on
the
> bottom FET of the first leg is also turned on. This is where the reverse
> recovery time of the body diode comes into play. The body diode of the
> bottom FET has to go into reverse bias (i.e. the minority carriers in the
> body-drain region have to be swept away and the depletion region
> established) before the top FET can block voltage. IF this process takes
> too long, then you will have shoot through currents. To keep things simple
> one would not want the Trr of the body diode to be any longer than the
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induce
> a spike in the gate of the other FET due to the parasitic Gate-Source
> capacitance. If your dv/dt is too large, then the induced spike might have
> enough amplitude to turn on the FET when it should be off. I have found
> that experimenting with various values of the gate drive resistance  (use
a
> parallel schottky to make sure you are not increasing turn off ) is the
> final answer to this multidimensional optimization.
> In some of my designs I have used a HIP4086 (3ph driver) and an
> APT10M19BVFRR to get about 25A of current (RMS) at 48VDC to run a 3ph bldc
> motor. I ended up using a dead time of 500ns and a gate drive resistance
of
> 20ohms (with a schottky in parallel).
> Good luck